| Message ID | 20221005144948.3421504-1-christoph.muellner@vrull.eu |
|---|---|
| State | New |
| Headers | show |
| Series | [v4] RISC-V: Add Zawrs ISA extension support | expand |
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > This patch adds support for the Zawrs ISA extension. > Given the current (incomplete) implementation of reservation sets > there seems to be no way to provide a full emulation of the WRS > instruction (wake on reservation set invalidation or timeout or > interrupt). Therefore, we just exit the TB and return to the main loop. > > The specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is frozen, but not ratified yet. > > Changes since v3: > * Remove "RFC" since the extension is frozen > * Rebase on master and fix integration issues > * Fix entry ordering in extension list > > Changes since v2: > * Rebase on master and resolve conflicts > * Adjustments according to a specification change > * Inline REQUIRE_ZAWRS() since it has only one user > > Changes since v1: > * Adding zawrs to the ISA string that is passed to the kernel > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 7 +++ > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 4 ++ > target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 64 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b29c88b9f0..b08ce94ba6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), > ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), > ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), > @@ -744,6 +745,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { > + error_setg(errp, "Zawrs extension requires A extension"); > + return; > + } > + > if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > return; > @@ -999,6 +1005,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > + DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b131fa8c8e..2b87966373 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -446,6 +446,7 @@ struct RISCVCPUConfig { > bool ext_svnapot; > bool ext_svpbmt; > bool ext_zdinx; > + bool ext_zawrs; > bool ext_zfh; > bool ext_zfhmin; > bool ext_zfinx; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d0253b8104..b7e7613ea2 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 > vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > > +# *** Zawrs Standard Extension *** > +wrs_nto 000000001101 00000 000 00000 1110011 > +wrs_sto 000000011101 00000 000 00000 1110011 > + > # *** RV32 Zba Standard Extension *** > sh1add 0010000 .......... 010 ..... 0110011 @r > sh2add 0010000 .......... 100 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc > new file mode 100644 > index 0000000000..f0da2fe50a > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc > @@ -0,0 +1,51 @@ > +/* > + * RISC-V translation routines for the RISC-V Zawrs Extension. > + * > + * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +static bool trans_wrs(DisasContext *ctx) > +{ > + if (!ctx->cfg_ptr->ext_zawrs) { > + return false; > + } > + > + /* > + * The specification says: > + * While stalled, an implementation is permitted to occasionally > + * terminate the stall and complete execution for any reason. > + * > + * So let's just exit TB and return to the main loop. > + */ > + > + /* Clear the load reservation (if any). */ > + tcg_gen_movi_tl(load_res, -1); > + > + gen_set_pc_imm(ctx, ctx->pc_succ_insn); > + tcg_gen_exit_tb(NULL, 0); > + ctx->base.is_jmp = DISAS_NORETURN; > + > + return true; > +} > + > +#define GEN_TRANS_WRS(insn) \ > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \ > +{ \ > + (void)a; \ > + return trans_wrs(ctx); \ > +} > + > +GEN_TRANS_WRS(wrs_nto) > +GEN_TRANS_WRS(wrs_sto) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index db123da5ec..e22de88e97 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1029,6 +1029,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvh.c.inc" > #include "insn_trans/trans_rvv.c.inc" > #include "insn_trans/trans_rvb.c.inc" > +#include "insn_trans/trans_rvzawrs.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_rvk.c.inc" > #include "insn_trans/trans_privileged.c.inc" > -- > 2.37.3 > >
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > This patch adds support for the Zawrs ISA extension. > Given the current (incomplete) implementation of reservation sets > there seems to be no way to provide a full emulation of the WRS > instruction (wake on reservation set invalidation or timeout or > interrupt). Therefore, we just exit the TB and return to the main loop. > > The specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is frozen, but not ratified yet. > > Changes since v3: > * Remove "RFC" since the extension is frozen > * Rebase on master and fix integration issues > * Fix entry ordering in extension list > > Changes since v2: > * Rebase on master and resolve conflicts > * Adjustments according to a specification change > * Inline REQUIRE_ZAWRS() since it has only one user > > Changes since v1: > * Adding zawrs to the ISA string that is passed to the kernel > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 7 +++ > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 4 ++ > target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 64 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b29c88b9f0..b08ce94ba6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), > ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), > ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), > @@ -744,6 +745,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { > + error_setg(errp, "Zawrs extension requires A extension"); > + return; > + } > + > if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > return; > @@ -999,6 +1005,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > + DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b131fa8c8e..2b87966373 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -446,6 +446,7 @@ struct RISCVCPUConfig { > bool ext_svnapot; > bool ext_svpbmt; > bool ext_zdinx; > + bool ext_zawrs; > bool ext_zfh; > bool ext_zfhmin; > bool ext_zfinx; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d0253b8104..b7e7613ea2 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 > vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > > +# *** Zawrs Standard Extension *** > +wrs_nto 000000001101 00000 000 00000 1110011 > +wrs_sto 000000011101 00000 000 00000 1110011 > + > # *** RV32 Zba Standard Extension *** > sh1add 0010000 .......... 010 ..... 0110011 @r > sh2add 0010000 .......... 100 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc > new file mode 100644 > index 0000000000..f0da2fe50a > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc > @@ -0,0 +1,51 @@ > +/* > + * RISC-V translation routines for the RISC-V Zawrs Extension. > + * > + * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +static bool trans_wrs(DisasContext *ctx) > +{ > + if (!ctx->cfg_ptr->ext_zawrs) { > + return false; > + } > + > + /* > + * The specification says: > + * While stalled, an implementation is permitted to occasionally > + * terminate the stall and complete execution for any reason. > + * > + * So let's just exit TB and return to the main loop. > + */ > + > + /* Clear the load reservation (if any). */ > + tcg_gen_movi_tl(load_res, -1); > + > + gen_set_pc_imm(ctx, ctx->pc_succ_insn); > + tcg_gen_exit_tb(NULL, 0); > + ctx->base.is_jmp = DISAS_NORETURN; > + > + return true; > +} > + > +#define GEN_TRANS_WRS(insn) \ > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \ > +{ \ > + (void)a; \ > + return trans_wrs(ctx); \ > +} > + > +GEN_TRANS_WRS(wrs_nto) > +GEN_TRANS_WRS(wrs_sto) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index db123da5ec..e22de88e97 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1029,6 +1029,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvh.c.inc" > #include "insn_trans/trans_rvv.c.inc" > #include "insn_trans/trans_rvb.c.inc" > +#include "insn_trans/trans_rvzawrs.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_rvk.c.inc" > #include "insn_trans/trans_privileged.c.inc" > -- > 2.37.3 > >
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > This patch adds support for the Zawrs ISA extension. > Given the current (incomplete) implementation of reservation sets > there seems to be no way to provide a full emulation of the WRS > instruction (wake on reservation set invalidation or timeout or > interrupt). Therefore, we just exit the TB and return to the main loop. > > The specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is frozen, but not ratified yet. > > Changes since v3: > * Remove "RFC" since the extension is frozen > * Rebase on master and fix integration issues > * Fix entry ordering in extension list > > Changes since v2: > * Rebase on master and resolve conflicts > * Adjustments according to a specification change > * Inline REQUIRE_ZAWRS() since it has only one user > > Changes since v1: > * Adding zawrs to the ISA string that is passed to the kernel > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> > --- > target/riscv/cpu.c | 7 +++ > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 4 ++ > target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 64 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b29c88b9f0..b08ce94ba6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), > ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), > ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), > @@ -744,6 +745,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { > + error_setg(errp, "Zawrs extension requires A extension"); > + return; > + } > + > if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > return; > @@ -999,6 +1005,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > + DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b131fa8c8e..2b87966373 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -446,6 +446,7 @@ struct RISCVCPUConfig { > bool ext_svnapot; > bool ext_svpbmt; > bool ext_zdinx; > + bool ext_zawrs; > bool ext_zfh; > bool ext_zfhmin; > bool ext_zfinx; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d0253b8104..b7e7613ea2 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 > vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > > +# *** Zawrs Standard Extension *** > +wrs_nto 000000001101 00000 000 00000 1110011 > +wrs_sto 000000011101 00000 000 00000 1110011 > + > # *** RV32 Zba Standard Extension *** > sh1add 0010000 .......... 010 ..... 0110011 @r > sh2add 0010000 .......... 100 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc > new file mode 100644 > index 0000000000..f0da2fe50a > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc > @@ -0,0 +1,51 @@ > +/* > + * RISC-V translation routines for the RISC-V Zawrs Extension. > + * > + * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +static bool trans_wrs(DisasContext *ctx) > +{ > + if (!ctx->cfg_ptr->ext_zawrs) { > + return false; > + } > + > + /* > + * The specification says: > + * While stalled, an implementation is permitted to occasionally > + * terminate the stall and complete execution for any reason. > + * > + * So let's just exit TB and return to the main loop. > + */ > + > + /* Clear the load reservation (if any). */ > + tcg_gen_movi_tl(load_res, -1); > + > + gen_set_pc_imm(ctx, ctx->pc_succ_insn); > + tcg_gen_exit_tb(NULL, 0); > + ctx->base.is_jmp = DISAS_NORETURN; > + > + return true; > +} > + > +#define GEN_TRANS_WRS(insn) \ > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \ > +{ \ > + (void)a; \ > + return trans_wrs(ctx); \ > +} There are tabs here picked up by checkpatch. I have replaced them with spaces Alistair > + > +GEN_TRANS_WRS(wrs_nto) > +GEN_TRANS_WRS(wrs_sto) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index db123da5ec..e22de88e97 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1029,6 +1029,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvh.c.inc" > #include "insn_trans/trans_rvv.c.inc" > #include "insn_trans/trans_rvb.c.inc" > +#include "insn_trans/trans_rvzawrs.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_rvk.c.inc" > #include "insn_trans/trans_privileged.c.inc" > -- > 2.37.3 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b29c88b9f0..b08ce94ba6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), @@ -744,6 +745,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; @@ -999,6 +1005,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), + DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b131fa8c8e..2b87966373 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -446,6 +446,7 @@ struct RISCVCPUConfig { bool ext_svnapot; bool ext_svpbmt; bool ext_zdinx; + bool ext_zawrs; bool ext_zfh; bool ext_zfhmin; bool ext_zfinx; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d0253b8104..b7e7613ea2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r +# *** Zawrs Standard Extension *** +wrs_nto 000000001101 00000 000 00000 1110011 +wrs_sto 000000011101 00000 000 00000 1110011 + # *** RV32 Zba Standard Extension *** sh1add 0010000 .......... 010 ..... 0110011 @r sh2add 0010000 .......... 100 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc new file mode 100644 index 0000000000..f0da2fe50a --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc @@ -0,0 +1,51 @@ +/* + * RISC-V translation routines for the RISC-V Zawrs Extension. + * + * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_wrs(DisasContext *ctx) +{ + if (!ctx->cfg_ptr->ext_zawrs) { + return false; + } + + /* + * The specification says: + * While stalled, an implementation is permitted to occasionally + * terminate the stall and complete execution for any reason. + * + * So let's just exit TB and return to the main loop. + */ + + /* Clear the load reservation (if any). */ + tcg_gen_movi_tl(load_res, -1); + + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + + return true; +} + +#define GEN_TRANS_WRS(insn) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \ +{ \ + (void)a; \ + return trans_wrs(ctx); \ +} + +GEN_TRANS_WRS(wrs_nto) +GEN_TRANS_WRS(wrs_sto) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index db123da5ec..e22de88e97 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1029,6 +1029,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvh.c.inc" #include "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" +#include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc"
This patch adds support for the Zawrs ISA extension. Given the current (incomplete) implementation of reservation sets there seems to be no way to provide a full emulation of the WRS instruction (wake on reservation set invalidation or timeout or interrupt). Therefore, we just exit the TB and return to the main loop. The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Note, that the Zawrs extension is frozen, but not ratified yet. Changes since v3: * Remove "RFC" since the extension is frozen * Rebase on master and fix integration issues * Fix entry ordering in extension list Changes since v2: * Rebase on master and resolve conflicts * Adjustments according to a specification change * Inline REQUIRE_ZAWRS() since it has only one user Changes since v1: * Adding zawrs to the ISA string that is passed to the kernel Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- target/riscv/cpu.c | 7 +++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++ target/riscv/translate.c | 1 + 5 files changed, 64 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc