| Message ID | 20220928050827.319293-3-wilfred.mallawa@opensource.wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add OpenTitan lifecycle controller | expand |
On Wed, Sep 28, 2022 at 3:13 PM Wilfred Mallawa <wilfred.mallawa@opensource.wdc.com> wrote: > > From: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > Connects the ibex lifecycle controller with opentitan, > with this change, we can now get past the lifecycle checks > in the boot rom. > > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/opentitan.c | 10 ++++++++-- > include/hw/riscv/opentitan.h | 2 ++ > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index be7ff1eea0..73a5cef694 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -122,6 +122,8 @@ static void lowrisc_ibex_soc_init(Object *obj) > > object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); > > + object_initialize_child(obj, "lifetime_ctrl", &s->lc, TYPE_IBEX_LC_CTRL); > + > for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { > object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], > TYPE_IBEX_SPI_HOST); > @@ -243,6 +245,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) > } > } > > + /* Life-Cycle Control */ > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lc), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lc), 0, memmap[IBEX_DEV_LC_CTRL].base); > + > create_unimplemented_device("riscv.lowrisc.ibex.gpio", > memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); > create_unimplemented_device("riscv.lowrisc.ibex.spi_device", > @@ -255,8 +263,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) > memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); > create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", > memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); > - create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", > - memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); > create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", > memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); > create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > index 6665cd5794..64b7f21339 100644 > --- a/include/hw/riscv/opentitan.h > +++ b/include/hw/riscv/opentitan.h > @@ -24,6 +24,7 @@ > #include "hw/char/ibex_uart.h" > #include "hw/timer/ibex_timer.h" > #include "hw/ssi/ibex_spi_host.h" > +#include "hw/misc/ibex_lc_ctrl.h" > #include "qom/object.h" > > #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" > @@ -44,6 +45,7 @@ struct LowRISCIbexSoCState { > SiFivePLICState plic; > IbexUartState uart; > IbexTimerState timer; > + IbexLCState lc; > IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; > > uint32_t resetvec; > -- > 2.37.3 > >
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index be7ff1eea0..73a5cef694 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -122,6 +122,8 @@ static void lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); + object_initialize_child(obj, "lifetime_ctrl", &s->lc, TYPE_IBEX_LC_CTRL); + for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], TYPE_IBEX_SPI_HOST); @@ -243,6 +245,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) } } + /* Life-Cycle Control */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lc), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lc), 0, memmap[IBEX_DEV_LC_CTRL].base); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi_device", @@ -255,8 +263,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); - create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", - memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 6665cd5794..64b7f21339 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -24,6 +24,7 @@ #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" #include "hw/ssi/ibex_spi_host.h" +#include "hw/misc/ibex_lc_ctrl.h" #include "qom/object.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" @@ -44,6 +45,7 @@ struct LowRISCIbexSoCState { SiFivePLICState plic; IbexUartState uart; IbexTimerState timer; + IbexLCState lc; IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; uint32_t resetvec;