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[2/2] target/i386: cmpxchg only overwrites ZF

Message ID 20220911222630.338330-3-pbonzini@redhat.com
State New
Headers show
Series target/i386: two fixes for cmpxchg | expand

Commit Message

Paolo Bonzini Sept. 11, 2022, 10:26 p.m. UTC
Do not set all the flags, they are untouched other than ZF.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/translate.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Richard Henderson Sept. 12, 2022, 7:58 a.m. UTC | #1
On 9/11/22 23:26, Paolo Bonzini wrote:
> Do not set all the flags, they are untouched other than ZF.

Um, no, second sentence:

# The ZF flag is set if the values in the destination operand and register
# AL, AX, or EAX are equal; otherwise it is
  cleared. The CF, PF, AF, SF,
# and OF flags are set according to the results of the comparison operation.


r~
diff mbox series

Patch

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 0e9237d627..488a617d14 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -5548,10 +5548,12 @@  static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                     gen_op_mov_reg_v(s, ot, R_EAX, oldv);
                 }
             }
-            tcg_gen_mov_tl(cpu_cc_src, oldv);
-            tcg_gen_mov_tl(s->cc_srcT, cmpv);
-            tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
-            set_cc_op(s, CC_OP_SUBB + ot);
+
+            gen_compute_eflags(s);
+            tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
+            tcg_gen_addi_tl(s->T0, cpu_cc_src, CC_Z);
+            tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src, oldv, cmpv, s->T0, cpu_cc_src);
+
             tcg_temp_free(oldv);
             tcg_temp_free(newv);
             tcg_temp_free(cmpv);