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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 39/42] hw/isa/piix: Unexport PIIXState Date: Thu, 1 Sep 2022 18:26:10 +0200 Message-Id: <20220901162613.6939-40-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The - deliberately exported - components can still be accessed via QOM properties. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 52 +++++++++++++++++++++++++++++++++ include/hw/southbridge/piix.h | 54 ----------------------------------- 2 files changed, 52 insertions(+), 54 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index e413d7e792..c503a6e836 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -26,20 +26,72 @@ #include "qemu/osdep.h" #include "qemu/range.h" #include "qapi/error.h" +#include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/dma/i8257.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/southbridge/piix.h" #include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" +#include "hw/pci/pci.h" +#include "hw/qdev-properties.h" +#include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" +#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define XEN_PIIX_NUM_PIRQS 128ULL +struct PIIXState { + PCIDevice dev; + + /* + * bitmap to track pic levels. + * The pic level is the logical OR of all the PCI irqs mapped to it + * So one PIC level is tracked by PIIX_NUM_PIRQS bits. + * + * PIRQ is mapped to PIC pins, we track it by + * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with + * pic_irq * PIIX_NUM_PIRQS + pirq + */ +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 +#error "unable to encode pic state in 64bit in pic_levels." +#endif + uint64_t pic_levels; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + + ISAPICState pic; + RTCState rtc; + PCIIDEState ide; + UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; + + /* Reset Control Register contents */ + uint8_t rcr; + + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ + MemoryRegion rcr_mem; + + bool has_acpi; + bool has_usb; + bool smm_enabled; +}; +typedef struct PIIXState PIIXState; + +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, + TYPE_PIIX3_PCI_DEVICE) + static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { qemu_set_irq(piix->pic.in_irqs[pic_irq], diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c9fa0f1aa6..0edc23710c 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -12,14 +12,6 @@ #ifndef HW_SOUTHBRIDGE_PIIX_H #define HW_SOUTHBRIDGE_PIIX_H -#include "hw/pci/pci.h" -#include "qom/object.h" -#include "hw/acpi/piix4.h" -#include "hw/ide/pci.h" -#include "hw/intc/i8259.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/usb/hcd-uhci.h" - /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 #define PIIX_PIRQCB 0x61 @@ -32,53 +24,7 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ - -struct PIIXState { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; - uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register contents */ - uint8_t rcr; - - /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ - MemoryRegion rcr_mem; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; -typedef struct PIIXState PIIXState; - #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) - #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa"