| Message ID | 20220728010000.2764631-1-alistair.francis@opensource.wdc.com |
|---|---|
| State | New |
| Headers | show |
On 7/27/22 17:59, Alistair Francis wrote: > From: Alistair Francis <alistair.francis@wdc.com> > > The following changes since commit 7b17a1a841fc2336eba53afade9cadb14bd3dd9a: > > Update version for v7.1.0-rc0 release (2022-07-26 18:03:16 -0700) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220728 > > for you to fetch changes up to 54f218363052be210e77d2ada8c0c1e51b3ad6cd: > > hw/intc: sifive_plic: Fix multi-socket plic configuraiton (2022-07-28 09:08:44 +1000) > > ---------------------------------------------------------------- > Sixth RISC-V PR for QEMU 7.1 > > This is a PR to go in for RC1. It fixes a segfault that occurs > when using multiple sockets on the RISC-V virt board. It also > includes a small fix to allow both Zmmul and M extensions. > > * Allow both Zmmul and M extension > * Fix multi-socket plic configuraiton Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ > > ---------------------------------------------------------------- > Atish Patra (1): > hw/intc: sifive_plic: Fix multi-socket plic configuraiton > > Palmer Dabbelt (1): > RISC-V: Allow both Zmmul and M > > hw/intc/sifive_plic.c | 4 ++-- > target/riscv/cpu.c | 5 ----- > 2 files changed, 2 insertions(+), 7 deletions(-) >
From: Alistair Francis <alistair.francis@wdc.com> The following changes since commit 7b17a1a841fc2336eba53afade9cadb14bd3dd9a: Update version for v7.1.0-rc0 release (2022-07-26 18:03:16 -0700) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220728 for you to fetch changes up to 54f218363052be210e77d2ada8c0c1e51b3ad6cd: hw/intc: sifive_plic: Fix multi-socket plic configuraiton (2022-07-28 09:08:44 +1000) ---------------------------------------------------------------- Sixth RISC-V PR for QEMU 7.1 This is a PR to go in for RC1. It fixes a segfault that occurs when using multiple sockets on the RISC-V virt board. It also includes a small fix to allow both Zmmul and M extensions. * Allow both Zmmul and M extension * Fix multi-socket plic configuraiton ---------------------------------------------------------------- Atish Patra (1): hw/intc: sifive_plic: Fix multi-socket plic configuraiton Palmer Dabbelt (1): RISC-V: Allow both Zmmul and M hw/intc/sifive_plic.c | 4 ++-- target/riscv/cpu.c | 5 ----- 2 files changed, 2 insertions(+), 7 deletions(-)