diff mbox series

[v11,6/6] target/riscv: Remove additional priv version check for mcountinhibit

Message ID 20220727064913.1041427-7-atishp@rivosinc.com
State New
Headers show
Series Improve PMU support | expand

Commit Message

Atish Patra July 27, 2022, 6:49 a.m. UTC 
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 8 --------
 1 file changed, 8 deletions(-)

Comments

Weiwei Li July 27, 2022, 8:22 a.m. UTC | #1 
在 2022/7/27 下午2:49, Atish Patra 写道:
> With .min_priv_version, additiona priv version check is uncessary
> for mcountinhibit read/write functions.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>   target/riscv/csr.c | 8 --------
>   1 file changed, 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ec6d7f022ad5..eac003d6b950 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1484,10 +1484,6 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
>   static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
>                                            target_ulong *val)
>   {
> -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> -        return RISCV_EXCP_ILLEGAL_INST;
> -    }
> -
>       *val = env->mcountinhibit;
>       return RISCV_EXCP_NONE;
>   }
> @@ -1498,10 +1494,6 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
>       int cidx;
>       PMUCTRState *counter;
>   
> -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> -        return RISCV_EXCP_ILLEGAL_INST;
> -    }
> -
>       env->mcountinhibit = val;
>   
>       /* Check if any other counter is also monitoring cycles/instructions */

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,
Weiwei Li
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ec6d7f022ad5..eac003d6b950 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1484,10 +1484,6 @@  static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
                                          target_ulong *val)
 {
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-
     *val = env->mcountinhibit;
     return RISCV_EXCP_NONE;
 }
@@ -1498,10 +1494,6 @@  static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
     int cidx;
     PMUCTRState *counter;
 
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-
     env->mcountinhibit = val;
 
     /* Check if any other counter is also monitoring cycles/instructions */