From patchwork Mon Jun 20 23:16:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 1645796 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20210112.gappssmtp.com header.i=@rivosinc-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=3WYK6n3h; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LRm3n43jSz9sGP for ; Tue, 21 Jun 2022 09:25:56 +1000 (AEST) Received: from localhost ([::1]:48308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3QmH-0004ej-CK for incoming@patchwork.ozlabs.org; Mon, 20 Jun 2022 19:25:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3QdE-00019V-Vs for qemu-devel@nongnu.org; Mon, 20 Jun 2022 19:16:33 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:34512) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o3Qd8-0006Rw-Ct for qemu-devel@nongnu.org; Mon, 20 Jun 2022 19:16:32 -0400 Received: by mail-pf1-x436.google.com with SMTP id t21so5223198pfq.1 for ; Mon, 20 Jun 2022 16:16:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DPXrtg50s/9/uRIX/w0Io/rE/ZDkMWNzoDdPwZ2XbSY=; b=3WYK6n3hsTeUmACjxanBzFs9OfHR1bn03VlYwcjWE8snnNax8J7FH8Bs41n62ENsc+ qBRGUlXvnK80t6U/IXph5cxV+3Lk+Wm/PUvtu7AtVnUKhncLPjp7LTiMH8He13xn1JOf AzTo1aeZtdYnaEhNEf985aTuqlM1hGaEhZMC+Orxrh6yG1nzL3frqj7WSfrczy6OCL3y jhK+oFarbWXUqrbnEL1PRzsQLxgP6asxfouFNR5ad71GDG/D+gngv8lY9bpcLdqg22rC LqIM+ELr4tgj60wHrGemXXh3uzYGbO3hqcxG92T/ycj0X73yszkgAaGtMd389NhoB2G5 +fKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DPXrtg50s/9/uRIX/w0Io/rE/ZDkMWNzoDdPwZ2XbSY=; b=jmn0fk8u+OCN9DL3gnBk2xrP9nB2gKvMklCHjBFmHgj74fjOchb54zzH9PZhe2yWuN hjcfJAn8QMoDQ74oT8Vhj32uD3XHJWPX1R9xKT4KzKup4oeAVqgYcHei7x9HCdQXD2sh udwB3fGHqRpoFBcEkOitl2pEjOv62CZ4+pS28V+d0biNw+8ZuymrhZ1cugkrtZWKLa5u BVcANC6kxixLUDzDQQ26R84YqNAm/WEN+QbdWyIJL9eTST1DifXbq3cbRl0f7XErZtpr msWZApSUfQongNiLCJ32bQTRdttf1gYxpOIxuGj4Kr4ONNbfR1/4ol4TyoiX+airIrvO oL7w== X-Gm-Message-State: AJIora/broCYpISyYs1dx8Qs808doWiTmcHWab+Xn/U320fhCRG1Tgi0 otkK5Af+Keae9ZPp15hb316NNQBXCiKrqQ== X-Google-Smtp-Source: AGRyM1u3rT3MqI6In76T8/XcyqcshP0wizFCll/4inPLJaupIcewZ5ivdbEJJ381mUD69IBQUBum8w== X-Received: by 2002:a05:6a00:1150:b0:524:dd4e:dba2 with SMTP id b16-20020a056a00115000b00524dd4edba2mr20411383pfm.41.1655766985449; Mon, 20 Jun 2022 16:16:25 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p2-20020a170902a40200b0015e8d4eb285sm9191008plq.207.2022.06.20.16.16.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 16:16:24 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org, frank.chang@sifive.com Subject: [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree Date: Mon, 20 Jun 2022 16:16:01 -0700 Message-Id: <20220620231603.2547260-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620231603.2547260-1-atishp@rivosinc.com> References: <20220620231603.2547260-1-atishp@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c | 28 +++++++++++++++++++++++ target/riscv/cpu.c | 1 + target/riscv/pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmu.h | 1 + 4 files changed, 87 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bc424dd2f523..0f3fdb4908b8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -29,6 +29,7 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -714,6 +715,32 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_phandles[socket] = aplic_s_phandle; } +static void create_fdt_socket_pmu(RISCVVirtState *s, + int socket, uint32_t *phandle, + uint32_t *intc_phandles) +{ + int cpu; + char *pmu_name; + uint32_t *pmu_cells; + MachineState *mc = MACHINE(s); + RISCVCPU hart = s->soc[socket].harts[0]; + + pmu_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); + + for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { + pmu_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); + pmu_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF); + } + + pmu_name = g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(mc->fdt, pmu_name); + qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + + g_free(pmu_name); + g_free(pmu_cells); +} + static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, @@ -759,6 +786,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, &intc_phandles[phandle_pos]); } } + create_fdt_socket_pmu(s, socket, phandle, intc_phandles); } if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d9e2aca12a9..69bbd9fff4e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1110,6 +1110,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) ISA_EDATA_ENTRY(zve64f, ext_zve64f), ISA_EDATA_ENTRY(zhinx, ext_zhinx), ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), + ISA_EDATA_ENTRY(sscofpmf, ext_sscofpmf), ISA_EDATA_ENTRY(svinval, ext_svinval), ISA_EDATA_ENTRY(svnapot, ext_svnapot), ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 34096941c0ce..59feb3c243dd 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -20,11 +20,68 @@ #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" +#include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ #define MAKE_32BIT_MASK(shift, length) \ (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) +/** + * To keep it simple, any event can be mapped to any programmable counters in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must continue + * to provide the correct value as well. Heterogeneous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[20] = {}; + uint32_t cmask; + + /* All the programmable counters can map to any event */ + cmask = MAKE_32BIT_MASK(3, num_ctrs); + + /** + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] = type + * event_idx[15:0] = code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] = cache_id + * event_idx.code[2:1] = op_id + * event_idx.code[0:0] = result_id + */ + + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] = cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] = cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] = cpu_to_be32(cmask); + + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 036653627f78..3004ce37b636 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx);