@@ -877,6 +877,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
+ DEFINE_PROP_BOOL("zawrs", RISCVCPU, cfg.ext_zawrs, true),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
@@ -380,6 +380,7 @@ struct RISCVCPUConfig {
bool ext_h;
bool ext_j;
bool ext_v;
+ bool ext_zawrs;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
@@ -111,6 +111,9 @@ wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+# *** Zawrs Instruction Extension ***
+wrs 000000010000 ..... 000 00000 1110011 @sfence_vm
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
new file mode 100644
@@ -0,0 +1,48 @@
+/*
+ * RISC-V translation routines for the RISC-V Zawrs Extension.
+ *
+ * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZAWRS(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zawrs) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_wrs(DisasContext *ctx, arg_sfence_vm *a)
+{
+ REQUIRE_ZAWRS(ctx);
+
+ /*
+ * We may continue if one or more of the following conditions are met:
+ * a) reservation set is invalid
+ * b) rs1 != 0 and X(rs1) < time CSR
+ * c) interrupt observed
+ *
+ * A reservation set can be invalidated by any store to a reserved
+ * memory location. However, that's currently not implemented in QEMU.
+ * So let's just exit the CPU loop and pretend that an interrupt occured.
+ */
+
+ /* Clear the load reservation (if any). */
+ tcg_gen_movi_tl(load_res, -1);
+
+ gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ return true;
+}
@@ -1005,6 +1005,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
+#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"