diff mbox series

[PULL,07/54] target/arm: Use tcg_constant in disas_exc

Message ID	20220428143958.2451229-8-peter.maydell@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 07/54] target/arm: Use tcg_constant in disas_exc Date: Thu, 28 Apr 2022 15:39:11 +0100 Message-Id: <20220428143958.2451229-8-peter.maydell@linaro.org> In-Reply-To: <20220428143958.2451229-1-peter.maydell@linaro.org> References: <20220428143958.2451229-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/54] target/arm: Use tcg_constant in gen_probe_access \| expand [PULL,01/54] target/arm: Use tcg_constant in gen_probe_access [PULL,02/54] target/arm: Use tcg_constant in gen_mte_check* [PULL,03/54] target/arm: Use tcg_constant in gen_exception* [PULL,04/54] target/arm: Use tcg_constant in gen_adc_CC [PULL,05/54] target/arm: Use tcg_constant in handle_msr_i [PULL,06/54] target/arm: Use tcg_constant in handle_sys [PULL,07/54] target/arm: Use tcg_constant in disas_exc [PULL,08/54] target/arm: Use tcg_constant in gen_compare_and_swap_pair [PULL,09/54] target/arm: Use tcg_constant in disas_ld_lit [PULL,10/54] target/arm: Use tcg_constant in disas_ldst_* [PULL,11/54] target/arm: Use tcg_constant in disas_add_sum_imm* [PULL,12/54] target/arm: Use tcg_constant in disas_movw_imm [PULL,13/54] target/arm: Use tcg_constant in shift_reg_imm [PULL,14/54] target/arm: Use tcg_constant in disas_cond_select [PULL,15/54] target/arm: Use tcg_constant in handle_{rev16,crc32} [PULL,16/54] target/arm: Use tcg_constant in disas_data_proc_2src [PULL,17/54] target/arm: Use tcg_constant in disas_fp* [PULL,18/54] target/arm: Use tcg_constant in simd shift expanders [PULL,19/54] target/arm: Use tcg_constant in simd fp/int conversion [PULL,20/54] target/arm: Use tcg_constant in 2misc expanders [PULL,21/54] target/arm: Use tcg_constant in balance of translate-a64.c [PULL,22/54] target/arm: Use tcg_constant for aa32 exceptions [PULL,23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn [PULL,24/54] target/arm: Use tcg_constant for gen_{msr,mrs} [PULL,25/54] target/arm: Use tcg_constant for vector shift expanders [PULL,26/54] target/arm: Use tcg_constant for do_coproc_insn [PULL,27/54] target/arm: Use tcg_constant for gen_srs [PULL,28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot [PULL,29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 [PULL,30/54] target/arm: Use tcg_constant for v7m MRS, MSR [PULL,31/54] target/arm: Use tcg_constant for TT, SAT, SMMLA [PULL,32/54] target/arm: Use tcg_constant in LDM, STM [PULL,33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE [PULL,34/54] target/arm: Use tcg_constant in trans_CPS_v7m [PULL,35/54] target/arm: Use tcg_constant in trans_CSEL [PULL,36/54] target/arm: Use tcg_constant for trans_INDEX_* [PULL,37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC [PULL,38/54] target/arm: Use tcg_constant in FCPY, CPY [PULL,39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active [PULL,40/54] target/arm: Use tcg_constant in do_clast_scalar [PULL,41/54] target/arm: Use tcg_constant in WHILE [PULL,42/54] target/arm: Use tcg_constant in LD1, ST1 [PULL,43/54] target/arm: Use tcg_constant in SUBR [PULL,44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm [PULL,45/54] target/arm: Use tcg_constant for predicate descriptors [PULL,46/54] target/arm: Use tcg_constant for do_brk{2,3} [PULL,47/54] target/arm: Use tcg_constant for vector descriptor [PULL,48/54] target/arm: Disable cryptographic instructions when neon is disabled [PULL,49/54] target/arm: Use field names for accessing DBGWCRn [PULL,50/54] hw/arm/smmuv3: Cache event fault record [PULL,51/54] hw/arm/smmuv3: Add space in guest error message [PULL,52/54] target/arm: Advertise support for FEAT_TTL [PULL,53/54] target/arm: Advertise support for FEAT_BBM level 2 [PULL,54/54] hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2

Commit Message

Peter Maydell April 28, 2022, 2:39 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5d1bccaf469..68e3b5c1f80 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2015,7 +2015,6 @@  static void disas_exc(DisasContext *s, uint32_t insn)
     int opc = extract32(insn, 21, 3);
     int op2_ll = extract32(insn, 0, 5);
     int imm16 = extract32(insn, 5, 16);
-    TCGv_i32 tmp;
 
     switch (opc) {
     case 0:
@@ -2050,9 +2049,7 @@  static void disas_exc(DisasContext *s, uint32_t insn)
                 break;
             }
             gen_a64_set_pc_im(s->pc_curr);
-            tmp = tcg_const_i32(syn_aa64_smc(imm16));
-            gen_helper_pre_smc(cpu_env, tmp);
-            tcg_temp_free_i32(tmp);
+            gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
             gen_ss_advance(s);
             gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
                                syn_aa64_smc(imm16), 3);