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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a05600c2dd000b0038ed449cbdbsm4312148wmh.3.2022.04.22.03.04.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 03:04:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/61] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count Date: Fri, 22 Apr 2022 11:03:34 +0100 Message-Id: <20220422100432.2288247-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422100432.2288247-1-peter.maydell@linaro.org> References: <20220422100432.2288247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Boards using the GICv3 need to configure it with both the total number of CPUs and also the sizes of all the memory regions which contain redistributors (one redistributor per CPU). At the moment the GICv3 checks that the number of CPUs specified is not too many to fit in the defined redistributor regions, but in fact the code assumes that the two match exactly. For instance when we set the GICR_TYPER.Last bit on the final redistributor in each region, we assume that we don't need to consider the possibility of a region being only half full of redistributors or even completely empty. We also assume in gicv3_redist_read() and gicv3_redist_write() that we can calculate the CPU index from the offset within the MemoryRegion and that this will always be in range. Fortunately all the board code sets the redistributor region sizes to exactly match the CPU count, so this isn't a visible bug. We could in theory make the GIC code handle non-full redistributor regions, or have it automatically reduce the provided region sizes to match the CPU count, but the simplest thing is just to strengthen the error check and insist that the CPU count and redistributor region size settings match exactly, since all the board code does that anyway. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220408141550.1271295-4-peter.maydell@linaro.org --- hw/intc/arm_gicv3_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 90204be25b6..c797c82786b 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -354,9 +354,9 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) for (i = 0; i < s->nb_redist_regions; i++) { rdist_capacity += s->redist_region_count[i]; } - if (rdist_capacity < s->num_cpu) { + if (rdist_capacity != s->num_cpu) { error_setg(errp, "Capacity of the redist regions(%d) " - "is less than number of vcpus(%d)", + "does not match the number of vcpus(%d)", rdist_capacity, s->num_cpu); return; }