target/rx: update PC correctly in wait instruction

`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.

This change fixes the wait instruction skipping the subsequent branch
when used in an idle loop like this:

    0:  wait
        bra.b 0b
        brk   // should be unreachable

Signed-off-by: Tomoaki Kawada <i@yvt.jp>
---
 target/rx/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

On 4/16/22 23:02, Tomoaki Kawada wrote:
> `cpu_pc` at this point does not necessary point to the current
> instruction (i.e., the wait instruction being translated), so it's
> incorrect to calculate the new value of `cpu_pc` based on this. It must
> be updated with `ctx->base.pc_next`, which contains the correct address
> of the next instruction.
> 
> This change fixes the wait instruction skipping the subsequent branch
> when used in an idle loop like this:
> 
>      0:  wait
>          bra.b 0b
>          brk   // should be unreachable
> 
> Signed-off-by: Tomoaki Kawada <i@yvt.jp>
> ---
>   target/rx/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 5db8f79a82..f8812e7a6c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -2281,7 +2281,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
>   static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
>   {
>       if (is_privileged(ctx, 1)) {
> -        tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
> +        tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
>           gen_helper_wait(cpu_env);
>       }
>       return true;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

On Sun, 17 Apr 2022 15:02:25 +0900,
Tomoaki Kawada wrote:
> 
> `cpu_pc` at this point does not necessary point to the current
> instruction (i.e., the wait instruction being translated), so it's
> incorrect to calculate the new value of `cpu_pc` based on this. It must
> be updated with `ctx->base.pc_next`, which contains the correct address
> of the next instruction.
> 
> This change fixes the wait instruction skipping the subsequent branch
> when used in an idle loop like this:
> 
>     0:  wait
>         bra.b 0b
>         brk   // should be unreachable
> 
> Signed-off-by: Tomoaki Kawada <i@yvt.jp>
> ---
>  target/rx/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 5db8f79a82..f8812e7a6c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -2281,7 +2281,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
>  static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
>  {
>      if (is_privileged(ctx, 1)) {
> -        tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
> +        tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
>          gen_helper_wait(cpu_env);
>      }
>      return true;
> -- 
> 2.35.1
> 

Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>

On 4/16/22 23:02, Tomoaki Kawada wrote:
> `cpu_pc` at this point does not necessary point to the current
> instruction (i.e., the wait instruction being translated), so it's
> incorrect to calculate the new value of `cpu_pc` based on this. It must
> be updated with `ctx->base.pc_next`, which contains the correct address
> of the next instruction.
> 
> This change fixes the wait instruction skipping the subsequent branch
> when used in an idle loop like this:
> 
>      0:  wait
>          bra.b 0b
>          brk   // should be unreachable
> 
> Signed-off-by: Tomoaki Kawada <i@yvt.jp>

Queued to target-rx-next.


r~