Message ID | 20220411125900.352028-1-fbarrat@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | target/ppc: Add two missing register callbacks on POWER10 | expand |
Frederic Barrat <fbarrat@linux.ibm.com> writes: > This patch adds tcg accessors for 2 SPRs which were missing on P10: > > - the TBU40 register is used to write the upper 40 bits of the > timebase register. It is used by kvm to update the timebase when > entering/exiting the guest on P9 and above. The missing definition was > causing erratic decrementer interrupts in a pseries/kvm guest running > in a powernv10/tcg host, typically resulting in hangs. > > - the missing DPDES SPR was found through code inspection. It exists > unchanged on P10. > > Both existed on previous versions of the processor and a bit of git > archaeology hints that they were added while the P10 model was already > being worked on so they may have simply fallen through the cracks. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> > --- > target/ppc/cpu_init.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 073fd10168..2e9a3ded54 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power5p_common_sprs(env); > register_power5p_lpar_sprs(env); > register_power5p_ear_sprs(env); > + register_power5p_tb_sprs(env); > register_power6_common_sprs(env); > register_power6_dbg_sprs(env); > register_power8_tce_address_control_sprs(env); > @@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power8_pmu_user_sprs(env); > register_power8_tm_sprs(env); > register_power8_pspb_sprs(env); > + register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > register_power8_book4_sprs(env);
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 4/11/22 09:59, Frederic Barrat wrote: > This patch adds tcg accessors for 2 SPRs which were missing on P10: > > - the TBU40 register is used to write the upper 40 bits of the > timebase register. It is used by kvm to update the timebase when > entering/exiting the guest on P9 and above. The missing definition was > causing erratic decrementer interrupts in a pseries/kvm guest running > in a powernv10/tcg host, typically resulting in hangs. > > - the missing DPDES SPR was found through code inspection. It exists > unchanged on P10. > > Both existed on previous versions of the processor and a bit of git > archaeology hints that they were added while the P10 model was already > being worked on so they may have simply fallen through the cracks. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- > target/ppc/cpu_init.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 073fd10168..2e9a3ded54 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power5p_common_sprs(env); > register_power5p_lpar_sprs(env); > register_power5p_ear_sprs(env); > + register_power5p_tb_sprs(env); > register_power6_common_sprs(env); > register_power6_dbg_sprs(env); > register_power8_tce_address_control_sprs(env); > @@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power8_pmu_user_sprs(env); > register_power8_tm_sprs(env); > register_power8_pspb_sprs(env); > + register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > register_power8_book4_sprs(env);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 073fd10168..2e9a3ded54 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power5p_common_sprs(env); register_power5p_lpar_sprs(env); register_power5p_ear_sprs(env); + register_power5p_tb_sprs(env); register_power6_common_sprs(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); @@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_pmu_user_sprs(env); register_power8_tm_sprs(env); register_power8_pspb_sprs(env); + register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); register_power8_book4_sprs(env);
This patch adds tcg accessors for 2 SPRs which were missing on P10: - the TBU40 register is used to write the upper 40 bits of the timebase register. It is used by kvm to update the timebase when entering/exiting the guest on P9 and above. The missing definition was causing erratic decrementer interrupts in a pseries/kvm guest running in a powernv10/tcg host, typically resulting in hangs. - the missing DPDES SPR was found through code inspection. It exists unchanged on P10. Both existed on previous versions of the processor and a bit of git archaeology hints that they were added while the P10 model was already being worked on so they may have simply fallen through the cracks. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- target/ppc/cpu_init.c | 2 ++ 1 file changed, 2 insertions(+)