| Message ID | 20220310202751.594961-3-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/s390x vector fixes | expand |
On 10/03/2022 21.27, Richard Henderson wrote: > The operands are output in the wrong order: the tcg selector > argument is first, whereas the s390x selector argument is last. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898 > Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec") > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/s390x/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index 508f1bccc7..3b185b3c96 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_bitsel_vec: > - tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); > + tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); > break; > > case INDEX_op_cmp_vec: Thank you very much, this indeed fixes the sha512 tet for me! Tested-by: Thomas Huth <thuth@redhat.com>
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 508f1bccc7..3b185b3c96 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_bitsel_vec: - tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); break; case INDEX_op_cmp_vec:
The operands are output in the wrong order: the tcg selector argument is first, whereas the s390x selector argument is last. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898 Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/s390x/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)