| Message ID | 20220212094418.93056-1-skrll@netbsd.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] hw/net: e1000e: Clear ICR on read when using non MSI-X interrupts | expand |
在 2022/2/12 下午5:44, Nick Hudson 写道: > In section 7.4.3 of the 82574 datasheet it states that > > "In systems that do not support MSI-X, reading the ICR > register clears it's bits..." > > Some OSes rely on this. > > Signed-off-by: Nick Hudson <skrll@netbsd.org> Applied. Thanks > --- > hw/net/e1000e_core.c | 5 +++++ > hw/net/trace-events | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c > index 8ae6fb7e14..2c51089a82 100644 > --- a/hw/net/e1000e_core.c > +++ b/hw/net/e1000e_core.c > @@ -2607,6 +2607,11 @@ e1000e_mac_icr_read(E1000ECore *core, int index) > core->mac[ICR] = 0; > } > > + if (!msix_enabled(core->owner)) { > + trace_e1000e_irq_icr_clear_nonmsix_icr_read(); > + core->mac[ICR] = 0; > + } > + > if ((core->mac[ICR] & E1000_ICR_ASSERTED) && > (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { > trace_e1000e_irq_icr_clear_iame(); > diff --git a/hw/net/trace-events b/hw/net/trace-events > index 643338f610..4c0ec3fda1 100644 > --- a/hw/net/trace-events > +++ b/hw/net/trace-events > @@ -221,6 +221,7 @@ e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" > e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" > e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" > e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" > +e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int" > e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" > e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" > e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 8ae6fb7e14..2c51089a82 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2607,6 +2607,11 @@ e1000e_mac_icr_read(E1000ECore *core, int index) core->mac[ICR] = 0; } + if (!msix_enabled(core->owner)) { + trace_e1000e_irq_icr_clear_nonmsix_icr_read(); + core->mac[ICR] = 0; + } + if ((core->mac[ICR] & E1000_ICR_ASSERTED) && (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { trace_e1000e_irq_icr_clear_iame(); diff --git a/hw/net/trace-events b/hw/net/trace-events index 643338f610..4c0ec3fda1 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -221,6 +221,7 @@ e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" +e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int" e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
In section 7.4.3 of the 82574 datasheet it states that "In systems that do not support MSI-X, reading the ICR register clears it's bits..." Some OSes rely on this. Signed-off-by: Nick Hudson <skrll@netbsd.org> --- hw/net/e1000e_core.c | 5 +++++ hw/net/trace-events | 1 + 2 files changed, 6 insertions(+)