| Message ID | 20220210123447.3933301-8-matheus.ferst@eldorado.org.br |
|---|---|
| State | New |
| Headers | show |
| Series | target/ppc: PowerISA Vector/VSX instruction batch | expand |
On 2/10/22 23:34, matheus.ferst@eldorado.org.br wrote: > From: Lucas Coutinho <lucas.coutinho@eldorado.org.br> > > Move the following instructions to decodetree: > vextsb2w: Vector Extend Sign Byte To Word > vextsh2w: Vector Extend Sign Halfword To Word > vextsb2d: Vector Extend Sign Byte To Doubleword > vextsh2d: Vector Extend Sign Halfword To Doubleword > vextsw2d: Vector Extend Sign Word To Doubleword > > Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br> > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > --- > target/ppc/helper.h | 5 ----- > target/ppc/insn32.decode | 8 ++++++++ > target/ppc/int_helper.c | 15 --------------- > target/ppc/translate/vmx-impl.c.inc | 25 ++++++++++++++++++++----- > target/ppc/translate/vmx-ops.c.inc | 5 ----- > 5 files changed, 28 insertions(+), 30 deletions(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 92595a42df..0084080fad 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -249,11 +249,6 @@ DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl) > DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl) > DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl) > DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl) > -DEF_HELPER_2(vextsb2w, void, avr, avr) > -DEF_HELPER_2(vextsh2w, void, avr, avr) > -DEF_HELPER_2(vextsb2d, void, avr, avr) > -DEF_HELPER_2(vextsh2d, void, avr, avr) > -DEF_HELPER_2(vextsw2d, void, avr, avr) > DEF_HELPER_2(vnegw, void, avr, avr) > DEF_HELPER_2(vnegd, void, avr, avr) > DEF_HELPER_2(vupkhpx, void, avr, avr) > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index c4796260b6..757791f0ac 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -419,6 +419,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX > VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN > VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN > > +## Vector Integer Arithmetic Instructions > + > +VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb > +VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb > +VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb > +VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb > +VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb > + > ## Vector Mask Manipulation Instructions > > MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb > diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c > index 79cde68f19..630fbc579a 100644 > --- a/target/ppc/int_helper.c > +++ b/target/ppc/int_helper.c > @@ -1768,21 +1768,6 @@ XXBLEND(W, 32) > XXBLEND(D, 64) > #undef XXBLEND > > -#define VEXT_SIGNED(name, element, cast) \ > -void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \ > -{ \ > - int i; \ > - for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ > - r->element[i] = (cast)b->element[i]; \ > - } \ > -} > -VEXT_SIGNED(vextsb2w, s32, int8_t) > -VEXT_SIGNED(vextsb2d, s64, int8_t) > -VEXT_SIGNED(vextsh2w, s32, int16_t) > -VEXT_SIGNED(vextsh2d, s64, int16_t) > -VEXT_SIGNED(vextsw2d, s64, int32_t) > -#undef VEXT_SIGNED > - > #define VNEG(name, element) \ > void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \ > { \ > diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc > index b7559cf94c..ec782c47ff 100644 > --- a/target/ppc/translate/vmx-impl.c.inc > +++ b/target/ppc/translate/vmx-impl.c.inc > @@ -1772,11 +1772,26 @@ GEN_VXFORM_TRANS(vclzw, 1, 30) > GEN_VXFORM_TRANS(vclzd, 1, 31) > GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) > GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) > -GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) > -GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) > -GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) > -GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) > -GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) > + > +static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, int vece, int s) > +{ > + REQUIRE_INSNS_FLAGS2(ctx, ISA300); > + REQUIRE_VECTOR(ctx); > + > + tcg_gen_gvec_shli(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb), > + s, 16, 16); > + tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrt), > + s, 16, 16); It would be better to collect this into a single composite gvec operation (x86 is especially bad with unsupported vector operation sizes). Use GVecGen3, provide the relevant .fni4/.fni8/.fniv functions and the vecop_list. We have elsewhere relied on 4 integer operations being expanded, when the vector op itself isn't supported, so you should be able to drop the .fnio out-of-line helper. r~
diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 92595a42df..0084080fad 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -249,11 +249,6 @@ DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl) DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl) DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl) DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl) -DEF_HELPER_2(vextsb2w, void, avr, avr) -DEF_HELPER_2(vextsh2w, void, avr, avr) -DEF_HELPER_2(vextsb2d, void, avr, avr) -DEF_HELPER_2(vextsh2d, void, avr, avr) -DEF_HELPER_2(vextsw2d, void, avr, avr) DEF_HELPER_2(vnegw, void, avr, avr) DEF_HELPER_2(vnegd, void, avr, avr) DEF_HELPER_2(vupkhpx, void, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index c4796260b6..757791f0ac 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -419,6 +419,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +## Vector Integer Arithmetic Instructions + +VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb +VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb +VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb +VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb +VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb + ## Vector Mask Manipulation Instructions MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 79cde68f19..630fbc579a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1768,21 +1768,6 @@ XXBLEND(W, 32) XXBLEND(D, 64) #undef XXBLEND -#define VEXT_SIGNED(name, element, cast) \ -void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \ -{ \ - int i; \ - for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ - r->element[i] = (cast)b->element[i]; \ - } \ -} -VEXT_SIGNED(vextsb2w, s32, int8_t) -VEXT_SIGNED(vextsb2d, s64, int8_t) -VEXT_SIGNED(vextsh2w, s32, int16_t) -VEXT_SIGNED(vextsh2d, s64, int16_t) -VEXT_SIGNED(vextsw2d, s64, int32_t) -#undef VEXT_SIGNED - #define VNEG(name, element) \ void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \ { \ diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index b7559cf94c..ec782c47ff 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1772,11 +1772,26 @@ GEN_VXFORM_TRANS(vclzw, 1, 30) GEN_VXFORM_TRANS(vclzd, 1, 31) GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) -GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) -GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) -GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) -GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) -GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) + +static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, int vece, int s) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_shli(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb), + s, 16, 16); + tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrt), + s, 16, 16); + + return true; +} + +TRANS(VEXTSB2W, do_vexts, MO_32, 24); +TRANS(VEXTSH2W, do_vexts, MO_32, 16); +TRANS(VEXTSB2D, do_vexts, MO_64, 56); +TRANS(VEXTSH2D, do_vexts, MO_64, 48); +TRANS(VEXTSW2D, do_vexts, MO_64, 32); + GEN_VXFORM_NOA_2(vctzb, 1, 24, 28) GEN_VXFORM_NOA_2(vctzh, 1, 24, 29) GEN_VXFORM_NOA_2(vctzw, 1, 24, 30) diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc index 914e68e5b0..6787327f56 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -216,11 +216,6 @@ GEN_VXFORM(vspltish, 6, 13), GEN_VXFORM(vspltisw, 6, 14), GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06), GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07), -GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10), -GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11), -GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18), -GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19), -GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A), GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C), GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D), GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),