Message ID | 20220113170036.1214238-1-clg@kaod.org |
---|---|
State | New |
Headers | show |
Series | [v2] ppc/ppc405: Fix TLB flushing | expand |
On 1/13/22 18:00, Cédric Le Goater wrote: > Commit cd0c6f473532 did not take into account 405 CPUs when adding > support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH > flag when the SPR_40x_PID is updated. > > Cc: Thomas Huth <thuth@redhat.com> > Cc: Christophe Leroy <christophe.leroy@csgroup.eu> > Cc: Fabiano Rosas <farosas@linux.ibm.com> > Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > > Changes in v2: > > - Rely on the SPR_40x_PID store helper to program the flush operation we need both. v3 in plan. I guess I want 405 to be fixed too rapidly :) Sorry for the noise. C.
diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f9c72dcd504d..08165184005c 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -708,6 +708,7 @@ DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_2(store_40x_pid, void, env, tl) DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 59df6952aea1..743215f51c36 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -664,6 +664,14 @@ static inline int booke_page_size_to_tlb(target_ulong page_size) #define PPC4XX_TLBLO_ATTR_MASK 0x000000FF #define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00 +void helper_store_40x_pid(CPUPPCState *env, target_ulong val) +{ + if (env->spr[SPR_40x_PID] != val) { + env->spr[SPR_40x_PID] = val; + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; + } +} + target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, target_ulong entry) { ppcemb_tlb_t *tlb; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 40232201bb0c..3ad1be60e71d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -894,7 +894,7 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); - gen_store_spr(SPR_40x_PID, t0); + gen_helper_store_40x_pid(cpu_env, t0); tcg_temp_free(t0); }
Commit cd0c6f473532 did not take into account 405 CPUs when adding support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH flag when the SPR_40x_PID is updated. Cc: Thomas Huth <thuth@redhat.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Fabiano Rosas <farosas@linux.ibm.com> Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") Signed-off-by: Cédric Le Goater <clg@kaod.org> --- Changes in v2: - Rely on the SPR_40x_PID store helper to program the flush operation target/ppc/helper.h | 1 + target/ppc/mmu_helper.c | 8 ++++++++ target/ppc/translate.c | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-)