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Thu, 23 Dec 2021 12:18:27 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c6:7ce4:b718:2cc0:32df:97ee]) by smtp.gmail.com with ESMTPSA id f20sm1185114vsl.31.2021.12.23.12.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Dec 2021 12:18:26 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 2/5] target/ppc/power8-pmu-insn-cnt: introduce inc_spr_if_cond() Date: Thu, 23 Dec 2021 17:18:09 -0300 Message-Id: <20211223201812.846495-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::935 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The code that increments a PMC is repetitive: check if a given register has a bit/mask set or cleared and increment the counter. inc_spr_if_cond() will help deal with this repetition. This patch also gives a sample of how the function works by incrementing PMC5, which is supposed to be incremented only if MMCR0_FC56 is not set. We've also removing the call from the helper since that would cause PMC5 to be counted twice. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 43 ++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index 6cdf2d2d88..3cfb801c69 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -10,6 +10,38 @@ * See the COPYING file in the top-level directory. */ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +/* + * This function increments a SPR 'spr' by 'inc_val' if a given + * register 'reg' has a bitmask 'mask' set (cond = TCG_COND_EQ) or + * not set (TCG_COND_NE). + */ +static void inc_spr_if_cond(int reg, uint64_t mask, TCGCond cond, + int spr, int inc_val) +{ + TCGCond exit_cond = tcg_invert_cond(cond); + TCGLabel *l_exit; + TCGv t0, t1; + + l_exit = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, reg); + tcg_gen_andi_tl(t0, t0, mask); + tcg_gen_brcondi_tl(exit_cond, t0, mask, l_exit); + + t1 = tcg_temp_new(); + gen_load_spr(t1, spr); + tcg_gen_addi_tl(t1, t1, inc_val); + gen_store_spr(spr, t1); + + gen_set_label(l_exit); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} +#endif /* #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ + #if defined(TARGET_PPC64) static void pmu_count_insns(DisasContext *ctx) { @@ -22,15 +54,8 @@ static void pmu_count_insns(DisasContext *ctx) } #if !defined(CONFIG_USER_ONLY) - /* - * The PMU insns_inc() helper stops the internal PMU timer if a - * counter overflows happens. In that case, if the guest is - * running with icount and we do not handle it beforehand, - * the helper can trigger a 'bad icount read'. - */ - gen_icount_io_start(ctx); - - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); + inc_spr_if_cond(SPR_POWER_MMCR0, MMCR0_FC56, TCG_COND_NE, + SPR_POWER_PMC5, ctx->base.num_insns); #else /* * User mode can read (but not write) PMC5 and start/stop