diff mbox series

[v2,1/2] target/hppa: Minor code movement

Message ID 20211213185610.1987974-2-f4bug@amsat.org
State New
Headers show
Series target/hppa: Fix deposit assert from trans_shrpw_imm | expand

Commit Message

Philippe Mathieu-Daudé Dec. 13, 2021, 6:56 p.m. UTC 
Move the 'a->r1 == 0' if ladder earlier, simply
to ease reviewing the next commit change.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/hppa/translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3b9744deb44..261e4c75c7c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3204,14 +3204,14 @@  static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
 
     dest = dest_gpr(ctx, a->t);
     t2 = load_gpr(ctx, a->r2);
-    if (a->r1 == a->r2) {
+    if (a->r1 == 0) {
+        tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
+    } else if (a->r1 == a->r2) {
         TCGv_i32 t32 = tcg_temp_new_i32();
         tcg_gen_trunc_reg_i32(t32, t2);
         tcg_gen_rotri_i32(t32, t32, sa);
         tcg_gen_extu_i32_reg(dest, t32);
         tcg_temp_free_i32(t32);
-    } else if (a->r1 == 0) {
-        tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
     } else {
         TCGv_reg t0 = tcg_temp_new();
         tcg_gen_extract_reg(t0, t2, sa, 32 - sa);