From patchwork Mon Dec 6 10:37:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1563882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J70PB4f0vz9s1l for ; Mon, 6 Dec 2021 21:42:22 +1100 (AEDT) Received: from localhost ([::1]:41266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1muBRs-0007lQ-E3 for incoming@patchwork.ozlabs.org; Mon, 06 Dec 2021 05:42:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1muBND-0001DD-T9; Mon, 06 Dec 2021 05:37:33 -0500 Received: from smtpout4.mo529.mail-out.ovh.net ([217.182.185.173]:47523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1muBN9-0001nR-Oy; Mon, 06 Dec 2021 05:37:31 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.108.16.246]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 1886ED01202F; Mon, 6 Dec 2021 11:37:18 +0100 (CET) Received: from kaod.org (37.59.142.95) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Mon, 6 Dec 2021 11:37:16 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-95G00137bd4e06-fdc9-404c-a7a2-f72e3be82659, 4EE5CA355A73348BB336A65EF5ADB9B11F7CB924) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: , Subject: [PATCH 05/15] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() Date: Mon, 6 Dec 2021 11:37:02 +0100 Message-ID: <20211206103712.1866296-6-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211206103712.1866296-1-clg@kaod.org> References: <20211206103712.1866296-1-clg@kaod.org> MIME-Version: 1.0 X-Originating-IP: [37.59.142.95] X-ClientProxiedBy: DAG1EX2.mxp5.local (172.16.2.2) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: f87cca31-c72c-48d5-8082-0dd70a4ffc7c X-Ovh-Tracer-Id: 16707510196142050156 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvuddrjeefgddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddrleehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass client-ip=217.182.185.173; envelope-from=clg@kaod.org; helo=smtpout4.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christophe Leroy , Thomas Huth , Daniel Henrique Barboza , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" It was introduced in commit b8d3f5d12642 ("Add flags to support PowerPC 405 bootinfos variations.") but since its value has always been set to '1'. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- hw/ppc/ppc405.h | 3 +-- hw/ppc/ppc405_boards.c | 2 +- hw/ppc/ppc405_uc.c | 8 +++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c58f739886a6..4cb77aca5690 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -56,8 +56,7 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index f1623aa622a6..2ac38c86a643 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -261,7 +261,7 @@ static void ref405ep_init(MachineState *machine) bd.bi_plb_busfreq = 33333333; bd.bi_pci_busfreq = 33333333; bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); + bdloc = ppc405_set_bootinfo(env, &bd); env->gpr[3] = bdloc; kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e14d61e9b899..6806d6be31d5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -41,8 +41,7 @@ #include "qapi/error.h" #include "trace.h" -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags) +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -81,9 +80,8 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); } n = 0x6A; - if (flags & 0x00000001) { - for (i = 0; i < 6; i++) - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); + for (i = 0; i < 6; i++) { + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); n += 4;