| Message ID | 20211130230123.781844-3-farosas@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | QEMU/openbios: PPC Software TLB support in the G4 family | expand |
On 12/1/21 00:01, Fabiano Rosas wrote: > The e600 CPU is a successor of the 7448 and like all the 7450s CPUs, > it has an optional software TLB feature. > > We have determined that there is no OS software support for the 7450 > software TLB available these days. See the previous commit for more > information. > > This patch disables the SPRs and instructions related to software TLB > from the e600 CPU. > > No functional change intended. These facilities should be used by the > OS in interrupt handlers for interrupts that QEMU never generates. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/cpu_init.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 509df35d09..962acf295f 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -2537,9 +2537,6 @@ static void init_excp_7450(CPUPPCState *env) > env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; > env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; > env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; > - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; > - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; > - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; > env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; > env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; > env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; > @@ -6643,7 +6640,6 @@ static void init_proc_e600(CPUPPCState *env) > /* Memory management */ > register_low_BATs(env); > register_high_BATs(env); > - register_74xx_soft_tlb(env, 128, 2); > init_excp_7450(env); > env->dcache_line_size = 32; > env->icache_line_size = 32; > @@ -6667,7 +6663,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) > PPC_CACHE_DCBA | PPC_CACHE_DCBZ | > PPC_MEM_SYNC | PPC_MEM_EIEIO | > PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > - PPC_MEM_TLBIA | PPC_74xx_TLB | > + PPC_MEM_TLBIA | > PPC_SEGMENT | PPC_EXTERN | > PPC_ALTIVEC; > pcc->insns_flags2 = PPC_NONE; >
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 509df35d09..962acf295f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2537,9 +2537,6 @@ static void init_excp_7450(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; @@ -6643,7 +6640,6 @@ static void init_proc_e600(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6667,7 +6663,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->insns_flags2 = PPC_NONE;
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs, it has an optional software TLB feature. We have determined that there is no OS software support for the 7450 software TLB available these days. See the previous commit for more information. This patch disables the SPRs and instructions related to software TLB from the e600 CPU. No functional change intended. These facilities should be used by the OS in interrupt handlers for interrupts that QEMU never generates. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu_init.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)