From patchwork Fri Nov 26 11:53:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1560075 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0tV14cYnz9t2p for ; Fri, 26 Nov 2021 22:55:21 +1100 (AEDT) Received: from localhost ([::1]:39396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqZp1-0004rr-Ab for incoming@patchwork.ozlabs.org; Fri, 26 Nov 2021 06:55:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqZnl-0003Nw-95 for qemu-devel@nongnu.org; Fri, 26 Nov 2021 06:54:02 -0500 Received: from 10.mo552.mail-out.ovh.net ([87.98.187.244]:40039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqZng-0007SK-7b for qemu-devel@nongnu.org; Fri, 26 Nov 2021 06:54:00 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.108.16.235]) by mo552.mail-out.ovh.net (Postfix) with ESMTPS id CF83C22449; Fri, 26 Nov 2021 11:53:54 +0000 (UTC) Received: from kaod.org (37.59.142.105) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Fri, 26 Nov 2021 12:53:54 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-105G00647682893-e44a-4181-bc85-bab942868ce8, B8303126CBA279BD35B7DF0844B381DDFAFB7782) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: , Subject: [PATCH v3 05/18] ppc/pnv: Add POWER10 quads Date: Fri, 26 Nov 2021 12:53:36 +0100 Message-ID: <20211126115349.2737605-6-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211126115349.2737605-1-clg@kaod.org> References: <20211126115349.2737605-1-clg@kaod.org> MIME-Version: 1.0 X-Originating-IP: [37.59.142.105] X-ClientProxiedBy: DAG1EX2.mxp5.local (172.16.2.2) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 1ba6ce8e-9a76-4bb9-bd1d-6943cb396fb1 X-Ovh-Tracer-Id: 14614743744237767532 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvuddrhedvgdefvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddtheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh Received-SPF: pass client-ip=87.98.187.244; envelope-from=clg@kaod.org; helo=10.mo552.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Daniel Henrique Barboza , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Frederic Barrat , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" and use a pnv_chip_power10_quad_realize() helper to avoid code duplication with P9. This still needs some refinements on the XSCOM registers handling in PnvQuad. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 3 +++ hw/ppc/pnv.c | 50 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 43 insertions(+), 10 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a299fbc7f25c..13495423283a 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -128,6 +128,9 @@ struct Pnv10Chip { Pnv9Psi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a186df3fee41..5c342e313329 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1370,6 +1370,21 @@ static void pnv_chip_power9_instance_init(Object *obj) chip->num_phbs = pcc->num_phbs; } +static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, + PnvCore *pnv_core) +{ + char eq_name[32]; + int core_id = CPU_CORE(pnv_core)->core_id; + + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); + object_initialize_child_with_props(OBJECT(chip), eq_name, eq, + sizeof(*eq), TYPE_PNV_QUAD, + &error_fatal, NULL); + + object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); + qdev_realize(DEVICE(eq), NULL, &error_fatal); +} + static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) { PnvChip *chip = PNV_CHIP(chip9); @@ -1379,18 +1394,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) chip9->quads = g_new0(PnvQuad, chip9->nr_quads); for (i = 0; i < chip9->nr_quads; i++) { - char eq_name[32]; PnvQuad *eq = &chip9->quads[i]; - PnvCore *pnv_core = chip->cores[i * 4]; - int core_id = CPU_CORE(pnv_core)->core_id; - - snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); - object_initialize_child_with_props(OBJECT(chip), eq_name, eq, - sizeof(*eq), TYPE_PNV_QUAD, - &error_fatal, NULL); - object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); - qdev_realize(DEVICE(eq), NULL, &error_fatal); + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); @@ -1606,6 +1612,24 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); } +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) +{ + PnvChip *chip = PNV_CHIP(chip10); + int i; + + chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); + chip10->quads = g_new0(PnvQuad, chip10->nr_quads); + + for (i = 0; i < chip10->nr_quads; i++) { + PnvQuad *eq = &chip10->quads[i]; + + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); + + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), + &eq->xscom_regs); + } +} + static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); @@ -1627,6 +1651,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) return; } + pnv_chip_power10_quad_realize(chip10, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* XIVE2 interrupt controller (POWER10) */ object_property_set_int(OBJECT(&chip10->xive), "ic-bar", PNV10_XIVE2_IC_BASE(chip), &error_fatal);