Message ID | 20211124183231.1503090-9-git@xen0n.name |
---|---|
State | New |
Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xen0n.name header.i=@xen0n.name header.a=rsa-sha256 header.s=mail header.b=o8OJhWZ5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=<UNKNOWN>) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Hzqqw2hVwz9sRN for <incoming@patchwork.ozlabs.org>; Thu, 25 Nov 2021 05:52:12 +1100 (AEDT) Received: from localhost ([::1]:39566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1mpxNK-0005gm-6s for incoming@patchwork.ozlabs.org; Wed, 24 Nov 2021 13:52:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <git@xen0n.name>) id 1mpx5M-0006N4-Nk for qemu-devel@nongnu.org; Wed, 24 Nov 2021 13:33:36 -0500 Received: from mail.xen0n.name ([115.28.160.31]:43478 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <git@xen0n.name>) id 1mpx5K-0004hA-Ie for qemu-devel@nongnu.org; Wed, 24 Nov 2021 13:33:36 -0500 Received: from ld50.lan (unknown [101.88.31.179]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id B61B460AF2; Thu, 25 Nov 2021 02:33:26 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1637778806; bh=CErMEkdepVZXKcmYTnltj6hmnjHlJAN3lTT1it71TrU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o8OJhWZ5yZrrgdXrQbcZTQkZUUgLUEESZupqPuEND1+xmBLTIYS8KUZEFwkj51Vqr ilX3jY4+qp+XfRr/bHVdjmvx0AbTCesdGh3kiUK12dP314NrcFNsvmS6JtLTTFRTWF vljGZcb8+NqkEsFkRUbnm80xJ6+4GV/dwdvImsWY= From: WANG Xuerui <git@xen0n.name> To: qemu-devel@nongnu.org Subject: [PATCH for-7.0 v8 08/31] tcg/loongarch64: Implement the memory barrier op Date: Thu, 25 Nov 2021 02:32:08 +0800 Message-Id: <20211124183231.1503090-9-git@xen0n.name> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211124183231.1503090-1-git@xen0n.name> References: <20211124183231.1503090-1-git@xen0n.name> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Peter Maydell <peter.maydell@linaro.org>, XiaoJuan Yang <yangxiaojuan@loongson.cn>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <f4bug@amsat.org>, Laurent Vivier <laurent@vivier.eu>, WANG Xuerui <git@xen0n.name>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Song Gao <gaosong@loongson.cn> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
LoongArch64 port of QEMU TCG
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diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index fbacaef862..f12955723d 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -234,3 +234,35 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, g_assert_not_reached(); } } + +#include "tcg-insn-defs.c.inc" + +/* + * TCG intrinsics + */ + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* Baseline LoongArch only has the full barrier, unfortunately. */ + tcg_out_opc_dbar(s, 0); +} + +/* + * Entry-points + */ + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + TCGArg a0 = args[0]; + + switch (opc) { + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + default: + g_assert_not_reached(); + } +}