@@ -285,15 +285,31 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
start_cycle_count_session(env);
}
} else {
- /*
- * No change in MMCR0_FC state but, if the PMU is running and
- * a change in one of the frozen counter bits is made, update
- * the PMCs with the cycles counted so far.
- */
if (!curr_FC) {
+ bool cycles_updated = false;
+
+ /*
+ * No change in MMCR0_FC state but, if the PMU is running and
+ * a change in one of the frozen counter bits is made, update
+ * the PMCs with the cycles counted so far.
+ */
if ((curr_value & MMCR0_FC14) != (value & MMCR0_FC14) ||
(curr_value & MMCR0_FC56) != (value & MMCR0_FC56)) {
pmu_update_cycles(env, curr_value);
+ cycles_updated = true;
+ }
+
+ /*
+ * If changes in the overflow bits were made, start a new
+ * cycle count session to restart the appropriate overflow
+ * timers.
+ */
+ if ((curr_value & MMCR0_PMC1CE) != (value & MMCR0_PMC1CE) ||
+ (curr_value & MMCR0_PMCjCE) != (value & MMCR0_PMCjCE)) {
+ if (!cycles_updated) {
+ pmu_update_cycles(env, curr_value);
+ }
+ start_cycle_count_session(env);
}
}
}
Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time. To support this scenario, track the overflow bits state when a write in MMCR0 is made in which the run state of the PMU (MMCR0_FC bit) didn't change and, if some overflow bit were changed in the middle of a cycle count session, restart it. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> --- target/ppc/power8-pmu.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-)