diff mbox series

[PULL,37/41] usb/uhci: Misc clean up

Message ID	20211102134240.3036524-38-f4bug@amsat.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PULL 37/41] usb/uhci: Misc clean up Date: Tue, 2 Nov 2021 14:42:36 +0100 Message-Id: <20211102134240.3036524-38-f4bug@amsat.org> In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= <f4bug@amsat.org>, Aurelien Jarno <aurelien@aurel32.net> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/41] MAINTAINERS: Add MIPS general architecture support entry \| expand [PULL,01/41] MAINTAINERS: Add MIPS general architecture support entry [PULL,02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware [PULL,03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware [PULL,04/41] target/mips: Fix MSA MADDV.B opcode [PULL,05/41] target/mips: Fix MSA MSUBV.B opcode [PULL,06/41] target/mips: Adjust style in msa_translate_init() [PULL,07/41] target/mips: Use dup_const() to simplify [PULL,08/41] target/mips: Have check_msa_access() return a boolean [PULL,09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum [PULL,10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v [PULL,11/41] target/mips: Convert MSA LDI opcode to decodetree [PULL,12/41] target/mips: Convert MSA I5 instruction format to decodetree [PULL,13/41] target/mips: Convert MSA BIT instruction format to decodetree [PULL,14/41] target/mips: Convert MSA SHF opcode to decodetree [PULL,15/41] target/mips: Convert MSA I8 instruction format to decodetree [PULL,16/41] target/mips: Convert MSA load/store instruction format to decodetree [PULL,17/41] target/mips: Convert MSA 2RF instruction format to decodetree [PULL,18/41] target/mips: Convert MSA FILL opcode to decodetree [PULL,19/41] target/mips: Convert MSA 2R instruction format to decodetree [PULL,20/41] target/mips: Convert MSA VEC instruction format to decodetree [PULL,21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) [PULL,22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) [PULL,23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) [PULL,24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) [PULL,25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) [PULL,26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) [PULL,27/41] target/mips: Convert MSA ELM instruction format to decodetree [PULL,28/41] target/mips: Convert MSA COPY_U opcode to decodetree [PULL,29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree [PULL,30/41] target/mips: Convert MSA MOVE.V opcode to decodetree [PULL,31/41] target/mips: Convert CFCMSA opcode to decodetree [PULL,32/41] target/mips: Convert CTCMSA opcode to decodetree [PULL,33/41] target/mips: Remove generic MSA opcode [PULL,34/41] target/mips: Remove one MSA unnecessary decodetree overlap group [PULL,35/41] target/mips: Fix Loongson-3A4000 MSAIR config register [PULL,36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU [PULL,37/41] usb/uhci: Misc clean up [PULL,38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device [PULL,39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq [PULL,40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts [PULL,41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"

Commit Message

Philippe Mathieu-Daudé Nov. 2, 2021, 1:42 p.m. UTC

From: BALATON Zoltan <balaton@eik.bme.hu>

Fix a comment for coding style so subsequent patch will not get
checkpatch error and simplify and shorten uhci_update_irq().

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <b68a57dfcf181e73272b4dc951f8cc6e76b0d182.1635161629.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/usb/hcd-uhci.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff mbox series

Patch

diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index 0cb02a64321..c557566ec26 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -290,7 +290,7 @@  static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
 
 static void uhci_update_irq(UHCIState *s)
 {
-    int level;
+    int level = 0;
     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
@@ -298,8 +298,6 @@  static void uhci_update_irq(UHCIState *s)
         (s->status & UHCI_STS_HSERR) ||
         (s->status & UHCI_STS_HCPERR)) {
         level = 1;
-    } else {
-        level = 0;
     }
     pci_set_irq(&s->dev, level);
 }
@@ -1170,8 +1168,7 @@  void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
 
     pci_conf[PCI_CLASS_PROG] = 0x00;
     /* TODO: reset value should be 0. */
-    pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
-
+    pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */
     pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
 
     if (s->masterbus) {