diff mbox series

[v2,25/32] target/mips: Convert MSA COPY_U opcode to decodetree

Message ID 20211027180730.1551932-26-f4bug@amsat.org
State New
Headers show
Series target/mips: Fully convert MSA opcodes to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Oct. 27, 2021, 6:07 p.m. UTC 
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.

Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Add NULL_IF_TARGET_MIPS32() macro, use array of 4 functions
---
 target/mips/tcg/msa.decode      |  1 +
 target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++-------------
 2 files changed, 41 insertions(+), 26 deletions(-)

Comments

Richard Henderson Oct. 27, 2021, 10:08 p.m. UTC | #1 
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
> decodetree.
> 
> Since the 'n' field is a constant value, use tcg_constant_i32()
> instead of a TCG temporary.
> 
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2: Add NULL_IF_TARGET_MIPS32() macro, use array of 4 functions
> ---
>   target/mips/tcg/msa.decode      |  1 +
>   target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++-------------
>   2 files changed, 41 insertions(+), 26 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index e701e507bfc..4e1d3caadc5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -165,6 +165,7 @@  BNZ                 010001 111 .. ..... ................    @bz
 
   SLDI              011110 0000 ...... ..... .....  011001  @elm_df
   SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
   INSVE             011110 0101 ...... ..... .....  011001  @elm_df
 
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fabc7f5538b..a2d7bbe912f 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -38,7 +38,6 @@  enum {
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
@@ -565,6 +564,46 @@  TRANS_MSA(SLDI,     trans_msa_elm_df, gen_helper_msa_sldi_df);
 TRANS_MSA(SPLATI,   trans_msa_elm_df, gen_helper_msa_splati_df);
 TRANS_MSA(INSVE,    trans_msa_elm_df, gen_helper_msa_insve_df);
 
+static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm_df *a,
+                              gen_helper_piii * const gen_msa[4])
+{
+    if (a->df < 0 || !gen_msa[a->df]) {
+        return false;
+    }
+
+    if (check_msa_enabled(ctx)) {
+        return true;
+    }
+
+    if (a->wd == 0) {
+        /* Treat as NOP. */
+        return true;
+    }
+
+    gen_msa[a->df](cpu_env,
+                   tcg_constant_i32(a->wd),
+                   tcg_constant_i32(a->ws),
+                   tcg_constant_i32(a->n));
+
+    return true;
+}
+
+#if defined(TARGET_MIPS64)
+#define NULL_IF_TARGET_MIPS32(function) function
+#else
+#define NULL_IF_TARGET_MIPS32(function) NULL
+#endif
+
+static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
+{
+    static gen_helper_piii * const gen_msa_copy_u[4] = {
+        gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h,
+        NULL_IF_TARGET_MIPS32(gen_helper_msa_copy_u_w), NULL
+    };
+
+    return trans_msa_elm_d64(ctx, a, gen_msa_copy_u);
+}
+
 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 {
 #define MASK_MSA_ELM(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -577,7 +616,6 @@  static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 
     switch (MASK_MSA_ELM(ctx->opcode)) {
     case OPC_COPY_S_df:
-    case OPC_COPY_U_df:
     case OPC_INSERT_df:
 #if !defined(TARGET_MIPS64)
         /* Double format valid only for MIPS64 */
@@ -585,11 +623,6 @@  static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
             gen_reserved_instruction(ctx);
             break;
         }
-        if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
-              (df == DF_WORD)) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
 #endif
         switch (MASK_MSA_ELM(ctx->opcode)) {
         case OPC_COPY_S_df:
@@ -608,25 +641,6 @@  static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
                 case DF_DOUBLE:
                     gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
                     break;
-#endif
-                default:
-                    assert(0);
-                }
-            }
-            break;
-        case OPC_COPY_U_df:
-            if (likely(wd != 0)) {
-                switch (df) {
-                case DF_BYTE:
-                    gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
-                    break;
-                case DF_HALF:
-                    gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
-                    break;
-#if defined(TARGET_MIPS64)
-                case DF_WORD:
-                    gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
-                    break;
 #endif
                 default:
                     assert(0);