diff mbox series

[30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree

Message ID 20211023214803.522078-31-f4bug@amsat.org
State New
Headers show
Series target/mips: Fully convert MSA opcodes to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Oct. 23, 2021, 9:48 p.m. UTC 
Convert the CFCMSA (Copy From Control MSA register) and
CTCMSA (Copy To Control MSA register) opcodes to decodetree.

Since they respectively overlap with the SLDI and SPLATI
opcodes, use decodetree overlap groups.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 10 +++-
 target/mips/tcg/msa_translate.c | 95 ++++++++++++---------------------
 2 files changed, 42 insertions(+), 63 deletions(-)

Comments

Richard Henderson Oct. 24, 2021, 9:15 p.m. UTC | #1 
On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> Convert the CFCMSA (Copy From Control MSA register) and
> CTCMSA (Copy To Control MSA register) opcodes to decodetree.
> 
> Since they respectively overlap with the SLDI and SPLATI
> opcodes, use decodetree overlap groups.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      | 10 +++-
>   target/mips/tcg/msa_translate.c | 95 ++++++++++++---------------------
>   2 files changed, 42 insertions(+), 63 deletions(-)

There are a couple of tcg_const_i32 that should be tcg_constant_i32, but otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1bde1983de3..52dac0fde6d 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -155,8 +155,14 @@  BNZ                 010001 111 .. ..... ................    @bz
   HSUB_S            011110 110.. ..... ..... .....  010101  @3r
   HSUB_U            011110 111.. ..... ..... .....  010101  @3r
 
-  SLDI              011110 0000 ...... ..... .....  011001  @elm_df
-  SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  {
+    CTCMSA          011110 0000111110  ..... .....  011001  @elm
+    SLDI            011110 0000 ...... ..... .....  011001  @elm_df
+  }
+  {
+    CFCMSA          011110 0001111110  ..... .....  011001  @elm
+    SPLATI          011110 0001 ...... ..... .....  011001  @elm_df
+  }
   {
     MOVE_V          011110 0010111110  ..... .....  011001  @elm
     COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b03cde964e0..51af6f39cc4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -20,19 +20,6 @@ 
 /* Include the auto-generated decoder.  */
 #include "decode-msa.c.inc"
 
-#define OPC_MSA (0x1E << 26)
-
-#define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
-    OPC_MSA_ELM     = 0x19 | OPC_MSA,
-};
-
-enum {
-    /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
-    OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-};
-
 static const char msaregnames[][6] = {
     "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
     "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
@@ -552,33 +539,46 @@  static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
     return true;
 }
 
-static void gen_msa_elm_3e(DisasContext *ctx)
+static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
 {
-#define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
-    uint8_t source = (ctx->opcode >> 11) & 0x1f;
-    uint8_t dest = (ctx->opcode >> 6) & 0x1f;
-    TCGv telm = tcg_temp_new();
-    TCGv_i32 tsr = tcg_const_i32(source);
-    TCGv_i32 tdt = tcg_const_i32(dest);
+    TCGv telm;
+    TCGv_i32 tdt;
 
-    switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
-    case OPC_CTCMSA:
-        gen_load_gpr(telm, source);
-        gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
-        break;
-    case OPC_CFCMSA:
-        gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
-        gen_store_gpr(telm, dest);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
+    if (!check_msa_access(ctx)) {
+        return false;
     }
 
+    telm = tcg_temp_new();
+    tdt = tcg_const_i32(a->wd);
+
+    gen_load_gpr(telm, a->ws);
+    gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
+
     tcg_temp_free(telm);
     tcg_temp_free_i32(tdt);
+
+    return true;
+}
+
+static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
+{
+    TCGv telm;
+    TCGv_i32 tsr;
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    telm = tcg_temp_new();
+    tsr = tcg_const_i32(a->ws);
+
+    gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
+    gen_store_gpr(telm, a->wd);
+
+    tcg_temp_free(telm);
     tcg_temp_free_i32(tsr);
+
+    return true;
 }
 
 static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
@@ -676,19 +676,6 @@  TRANS_DF_D64(COPY_S,    trans_msa_elm_d64, gen_helper_msa_copy_s);
 TRANS_DF_W64(COPY_U,    trans_msa_elm_d64, gen_helper_msa_copy_u);
 TRANS_DF_D64(INSERT,    trans_msa_elm_d64, gen_helper_msa_insert);
 
-static void gen_msa_elm(DisasContext *ctx)
-{
-    uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-
-    if (dfn == 0x3E) {
-        /* CTCMSA, CFCMSA */
-        gen_msa_elm_3e(ctx);
-        return;
-    }
-
-    gen_reserved_instruction(ctx);
-}
-
 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
                           enum CPUMIPSMSADataFormat df_base,
                           void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
@@ -880,21 +867,7 @@  TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
 static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
-    uint32_t opcode = ctx->opcode;
-
-    if (!check_msa_access(ctx)) {
-        return false;
-    }
-
-    switch (MASK_MSA_MINOR(opcode)) {
-    case OPC_MSA_ELM:
-        gen_msa_elm(ctx);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
+    gen_reserved_instruction(ctx);
 
     return true;
 }