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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id m15sm12369083wmq.0.2021.10.23.14.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Oct 2021 14:50:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Date: Sat, 23 Oct 2021 23:47:54 +0200 Message-Id: <20211023214803.522078-25-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luis Pires , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 37 +++------------------------------ 2 files changed, 6 insertions(+), 34 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 4a9cf85fa7a..1d6fd86ef3d 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -80,6 +80,9 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + BINSL 011110 110.. ..... ..... ..... 001101 @3r + BINSR 011110 111.. ..... ..... ..... 001101 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index e1da532e5c9..1b69ec149a5 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -78,12 +78,10 @@ enum { OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12, OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14, - OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14, - OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12, @@ -518,6 +516,9 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, return true; } +TRANS_DF_E(BINSL, trans_msa_3r, gen_helper_msa_binsl); +TRANS_DF_E(BINSR, trans_msa_3r, gen_helper_msa_binsr); + TRANS_DF_B(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_B(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_B(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); @@ -548,38 +549,6 @@ static void gen_msa_3r(DisasContext *ctx) TCGv_i32 twt = tcg_const_i32(wt); switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; case OPC_BCLR_df: switch (df) { case DF_BYTE: