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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id s9sm14187283wmj.39.2021.10.23.14.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Oct 2021 14:49:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Date: Sat, 23 Oct 2021 23:47:52 +0200 Message-Id: <20211023214803.522078-23-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luis Pires , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 6 ++++++ target/mips/tcg/msa_translate.c | 35 ++++++++++++++++++++++----------- 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 28b7a71d930..ca0fd568560 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -24,6 +24,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0 +@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r @3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst @@ -79,6 +80,11 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + SLD 011110 000 .. ..... ..... ..... 010100 @3r + SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + + VSHF 011110 000 .. ..... ..... ..... 010101 @3r + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf FCUN 011110 0001 . ..... ..... ..... 011010 @3rf FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 4543b7abdfb..0c7055c68bd 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,15 +45,12 @@ enum { OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12, OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15, OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12, OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14, OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E, @@ -469,6 +466,29 @@ TRANS_MSA(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); +static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a, + void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tdf = tcg_constant_i32(a->df); + TCGv_i32 twd = tcg_const_i32(a->wd); + TCGv_i32 tws = tcg_const_i32(a->ws); + TCGv_i32 twt = tcg_const_i32(a->wt); + + gen_msa_3r_df(cpu_env, tdf, twd, tws, twt); + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + + return true; +} + +TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df); +TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df); + +TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1219,12 +1239,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBV_df: switch (df) { case DF_BYTE: @@ -1257,9 +1271,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: switch (df) { case DF_BYTE: