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[50.253.99.174]) by smtp.gmail.com with ESMTPSA id q7sm1133951ilv.48.2021.10.19.09.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 09:45:28 -0700 (PDT) From: Warner Losh To: qemu-devel@nongnu.org Subject: [PATCH 22/24] bsd-user/arm/target_arch_signal.h: arm set_mcontext Date: Tue, 19 Oct 2021 10:44:45 -0600 Message-Id: <20211019164447.16359-23-imp@bsdimp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211019164447.16359-1-imp@bsdimp.com> References: <20211019164447.16359-1-imp@bsdimp.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::134; envelope-from=imp@bsdimp.com; helo=mail-il1-x134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stacey Son , qemu-trivial@nongnu.org, Klye Evans , Michael Tokarev , Laurent Vivier , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the machine context to the CPU state. Signed-off-by: Stacey Son Signed-off-by: Klye Evans Signed-off-by: Warner Losh Reviewed-by: Kyle Evans --- bsd-user/arm/target_arch_signal.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/bsd-user/arm/target_arch_signal.h b/bsd-user/arm/target_arch_signal.h index 302fdc2846..1d051af9ae 100644 --- a/bsd-user/arm/target_arch_signal.h +++ b/bsd-user/arm/target_arch_signal.h @@ -201,4 +201,35 @@ static inline abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, return err; } +/* Compare to arm/arm/machdep.c set_mcontext() */ +static inline abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, + int srflag) +{ + int err = 0; + const uint32_t *gr = mcp->__gregs; + uint32_t cpsr; + + regs->regs[0] = tswap32(gr[TARGET_REG_R0]); + regs->regs[1] = tswap32(gr[TARGET_REG_R1]); + regs->regs[2] = tswap32(gr[TARGET_REG_R2]); + regs->regs[3] = tswap32(gr[TARGET_REG_R3]); + regs->regs[4] = tswap32(gr[TARGET_REG_R4]); + regs->regs[5] = tswap32(gr[TARGET_REG_R5]); + regs->regs[6] = tswap32(gr[TARGET_REG_R6]); + regs->regs[7] = tswap32(gr[TARGET_REG_R7]); + regs->regs[8] = tswap32(gr[TARGET_REG_R8]); + regs->regs[9] = tswap32(gr[TARGET_REG_R9]); + regs->regs[10] = tswap32(gr[TARGET_REG_R10]); + regs->regs[11] = tswap32(gr[TARGET_REG_R11]); + regs->regs[12] = tswap32(gr[TARGET_REG_R12]); + + regs->regs[13] = tswap32(gr[TARGET_REG_SP]); + regs->regs[14] = tswap32(gr[TARGET_REG_LR]); + regs->regs[15] = tswap32(gr[TARGET_REG_PC]); + cpsr = tswap32(gr[TARGET_REG_CPSR]); + cpsr_write(regs, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr); + + return err; +} + #endif /* !_TARGET_ARCH_SIGNAL_H_ */