diff mbox series

[02/13] target/riscv: Create RISCVMXL enumeration

Message ID 20211007174722.929993-3-richard.henderson@linaro.org
State New
Headers show
Series target/riscv: Rationalize XLEN and operand length | expand

Commit Message

Richard Henderson Oct. 7, 2021, 5:47 p.m. UTC 
Move the MXL_RV* defines to enumerators.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_bits.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Alistair Francis Oct. 11, 2021, 11:28 p.m. UTC | #1 
On Fri, Oct 8, 2021 at 3:47 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move the MXL_RV* defines to enumerators.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_bits.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..e248c6bf6d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -364,9 +364,11 @@
>  #define MISA32_MXL          0xC0000000
>  #define MISA64_MXL          0xC000000000000000ULL
>
> -#define MXL_RV32            1
> -#define MXL_RV64            2
> -#define MXL_RV128           3
> +typedef enum {
> +    MXL_RV32  = 1,
> +    MXL_RV64  = 2,
> +    MXL_RV128 = 3,
> +} RISCVMXL;
>
>  /* sstatus CSR bits */
>  #define SSTATUS_UIE         0x00000001
> --
> 2.25.1
>
>
LIU Zhiwei Oct. 13, 2021, 12:18 p.m. UTC | #2 
On 2021/10/8 上午1:47, Richard Henderson wrote:
> Move the MXL_RV* defines to enumerators.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>

Zhiwei
> ---
>   target/riscv/cpu_bits.h | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..e248c6bf6d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -364,9 +364,11 @@
>   #define MISA32_MXL          0xC0000000
>   #define MISA64_MXL          0xC000000000000000ULL
>   
> -#define MXL_RV32            1
> -#define MXL_RV64            2
> -#define MXL_RV128           3
> +typedef enum {
> +    MXL_RV32  = 1,
> +    MXL_RV64  = 2,
> +    MXL_RV128 = 3,
> +} RISCVMXL;
>   
>   /* sstatus CSR bits */
>   #define SSTATUS_UIE         0x00000001
diff mbox series

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@ 
 #define MISA32_MXL          0xC0000000
 #define MISA64_MXL          0xC000000000000000ULL
 
-#define MXL_RV32            1
-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;
 
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001