From patchwork Sat Sep 25 17:30:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 1532796 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xen0n.name header.i=@xen0n.name header.a=rsa-sha256 header.s=mail header.b=r+DHhp+t; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HGx8z6JzPz9t4b for ; Sun, 26 Sep 2021 03:44:03 +1000 (AEST) Received: from localhost ([::1]:35114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mUBiT-000355-JZ for incoming@patchwork.ozlabs.org; Sat, 25 Sep 2021 13:44:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mUBWL-0002Wp-Nm for qemu-devel@nongnu.org; Sat, 25 Sep 2021 13:31:29 -0400 Received: from [115.28.160.31] (port=57206 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mUBWH-0005U8-G4 for qemu-devel@nongnu.org; Sat, 25 Sep 2021 13:31:28 -0400 Received: from ld50.lan (unknown [101.88.29.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id B5B1060B41; Sun, 26 Sep 2021 01:30:55 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632591055; bh=761/xkxZRmzusdo2RzJAhC2ld/h5Mtv5Q7yJCSj0B38=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r+DHhp+t81Y9Kd+SFDPnxAxpKWeXgFHqcGMojCsVUt04GH5fpjoDXqDZ2io1tJiNp KooDXVgJ/6js6YkzuVjHhvpioh+M7Nyllu5Kry5Is9jEqHs/i7vRuYdrb/Fm8GL/yc nLPiy96BekIyBCwv3MjgEdn0/5Lp6WlzgMxjfRk4= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops Date: Sun, 26 Sep 2021 01:30:19 +0800 Message-Id: <20210925173032.2434906-18-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210925173032.2434906-1-git@xen0n.name> References: <20210925173032.2434906-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , XiaoJuan Yang , Richard Henderson , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , WANG Xuerui , Laurent Vivier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 2 ++ tcg/loongarch64/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 42f8e28741..4b8ce85897 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -18,6 +18,8 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) C_O1_I2(r, r, rU) C_O1_I2(r, r, rW) C_O1_I2(r, 0, rZ) +C_O1_I2(r, rZ, rN) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d0a24cc009..0e6b241097 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -687,6 +687,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_add_i32: + if (c2) { + tcg_out_opc_addi_w(s, a0, a1, a2); + } else { + tcg_out_opc_add_w(s, a0, a1, a2); + } + break; + case INDEX_op_add_i64: + if (c2) { + tcg_out_opc_addi_d(s, a0, a1, a2); + } else { + tcg_out_opc_add_d(s, a0, a1, a2); + } + break; + + case INDEX_op_sub_i32: + if (c2) { + tcg_out_opc_addi_w(s, a0, a1, -a2); + } else { + tcg_out_opc_sub_w(s, a0, a1, a2); + } + break; + case INDEX_op_sub_i64: + if (c2) { + tcg_out_opc_addi_d(s, a0, a1, -a2); + } else { + tcg_out_opc_sub_d(s, a0, a1, a2); + } + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -748,6 +778,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotr_i64: return C_O1_I2(r, r, ri); + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return C_O1_I2(r, r, rI); + case INDEX_op_and_i32: case INDEX_op_and_i64: case INDEX_op_nor_i32: @@ -770,6 +804,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* Must deposit into the same register as input */ return C_O1_I2(r, 0, rZ); + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return C_O1_I2(r, rZ, rN); + default: g_assert_not_reached(); }