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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id o17sm7541189wrj.96.2021.09.24.02.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Sep 2021 02:40:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v6 18/40] target/arm: Restrict has_work() handler to sysemu and TCG Date: Fri, 24 Sep 2021 11:38:25 +0200 Message-Id: <20210924093847.1014331-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210924093847.1014331-1-f4bug@amsat.org> References: <20210924093847.1014331-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM TCG CPUs" , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict arm_cpu_has_work() and has_work() handler to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 4 +++- target/arm/cpu.c | 7 +++++-- target/arm/cpu_tcg.c | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 864b5ad4cdf..29bb815100d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -175,9 +175,11 @@ void arm_translate_init(void); #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -#endif /* CONFIG_TCG */ +#if !defined(CONFIG_USER_ONLY) bool arm_cpu_has_work(CPUState *cs); +#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG */ /** * aarch64_sve_zcr_get_valid_len: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4b08f717f64..53c478171ac 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -74,8 +74,8 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] = tb->pc; } } -#endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -86,6 +86,9 @@ bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); } +#endif /* !CONFIG_USER_ONLY */ + +#endif /* CONFIG_TCG */ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) @@ -2035,6 +2038,7 @@ static const struct TCGCPUOps arm_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, #if !defined(CONFIG_USER_ONLY) + .has_work = arm_cpu_has_work, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, @@ -2059,7 +2063,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; - cc->has_work = arm_cpu_has_work; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9a0927ad5d0..7d0d9fcbc79 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, #if !defined(CONFIG_USER_ONLY) + .has_work = arm_cpu_has_work, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, @@ -920,7 +921,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifdef CONFIG_TCG - cc->has_work = arm_cpu_has_work; cc->tcg_ops = &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */