| Message ID | 20210921201915.601245-15-git@xen0n.name |
|---|---|
| State | New |
| Headers | show |
| Series | LoongArch64 port of QEMU TCG | expand |
On 9/21/21 1:18 PM, WANG Xuerui wrote: > + case INDEX_op_bswap32_i32: > + /* All 32-bit values are computed sign-extended in the register. */ > + a2 = TCG_BSWAP_OS; > + /* fallthrough */ > + case INDEX_op_bswap32_i64: > + tcg_out_opc_revb_2w(s, a0, a1); > + if (a2 & TCG_BSWAP_OS) { > + tcg_out_ext32s(s, a0, a0); > + } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { > + tcg_out_ext32u(s, a0, a0); > + } > + break; Looks good so far, so: Reviewed-by: Richard Henderson <richard.henderson@linaro.org> We'll also want INDEX_op_bswap16_{i32,i64}. This should look just like bswap32_i64, except with revb_2h and ext16{s,u}. r~
Hi Richard, On 9/22/21 22:54, Richard Henderson wrote: > On 9/21/21 1:18 PM, WANG Xuerui wrote: >> + case INDEX_op_bswap32_i32: >> + /* All 32-bit values are computed sign-extended in the >> register. */ >> + a2 = TCG_BSWAP_OS; >> + /* fallthrough */ >> + case INDEX_op_bswap32_i64: >> + tcg_out_opc_revb_2w(s, a0, a1); >> + if (a2 & TCG_BSWAP_OS) { >> + tcg_out_ext32s(s, a0, a0); >> + } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == >> TCG_BSWAP_OZ) { >> + tcg_out_ext32u(s, a0, a0); >> + } >> + break; > > Looks good so far, so: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > We'll also want INDEX_op_bswap16_{i32,i64}. This should look just > like bswap32_i64, except with revb_2h and ext16{s,u}. Thanks for the suggestion; I'll add these in v3, since they're relatively light-weight to implement. > > > r~
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 27066960cf..e7b5f2c5ab 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -508,6 +508,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); break; + case INDEX_op_bswap32_i32: + /* All 32-bit values are computed sign-extended in the register. */ + a2 = TCG_BSWAP_OS; + /* fallthrough */ + case INDEX_op_bswap32_i64: + tcg_out_opc_revb_2w(s, a0, a1); + if (a2 & TCG_BSWAP_OS) { + tcg_out_ext32s(s, a0, a0); + } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { + tcg_out_ext32u(s, a0, a0); + } + break; + + case INDEX_op_bswap64_i64: + tcg_out_opc_revb_d(s, a0, a1); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -539,6 +556,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_not_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: return C_O1_I1(r, r); case INDEX_op_andc_i32:
Signed-off-by: WANG Xuerui <git@xen0n.name> --- tcg/loongarch64/tcg-target.c.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)