mbox

[PULL,v2,00/21] riscv-to-apply queue

Message ID 20210921065412.312381-1-alistair.francis@opensource.wdc.com
State New
Headers show

Pull-request

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210921

Message

Alistair Francis Sept. 21, 2021, 6:53 a.m. UTC 
From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac:

  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-09-20 16:17:05 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210921

for you to fetch changes up to ed481d9837250aa682f5156528bc923e1b214f76:

  hw/riscv: opentitan: Correct the USB Dev address (2021-09-21 12:10:47 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 6.2

 - ePMP CSR address updates
 - Convert internal interrupts to use QEMU GPIO lines
 - SiFive PWM support
 - Support for RISC-V ACLINT
 - SiFive PDMA fixes
 - Update to u-boot instructions for sifive_u
 - mstatus.SD bug fix for hypervisor extensions
 - OpenTitan fix for USB dev address

----------------------------------------------------------------
Alistair Francis (9):
      target/riscv: Update the ePMP CSR address
      target/riscv: Expose interrupt pending bits as GPIO lines
      hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
      hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
      hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
      hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
      hw/timer: Add SiFive PWM support
      sifive_u: Connect the SiFive PWM device
      hw/riscv: opentitan: Correct the USB Dev address

Anup Patel (4):
      hw/intc: Rename sifive_clint sources to riscv_aclint sources
      hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
      hw/riscv: virt: Re-factor FDT generation
      hw/riscv: virt: Add optional ACLINT support to virt machine

Bin Meng (2):
      docs/system/riscv: sifive_u: Update U-Boot instructions
      target/riscv: csr: Rename HCOUNTEREN_CY and friends

Frank Chang (4):
      hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
      hw/dma: sifive_pdma: claim bit must be set before DMA transactions
      hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
      target/riscv: Backup/restore mstatus.SD bit when virtual register swapped

Green Wan (1):
      hw/dma: sifive_pdma: allow non-multiple transaction size transactions

LIU Zhiwei (1):
      target/riscv: Fix satp write

 docs/system/riscv/sifive_u.rst |  50 ++--
 docs/system/riscv/virt.rst     |  10 +
 include/hw/intc/ibex_plic.h    |   2 +
 include/hw/intc/riscv_aclint.h |  80 +++++
 include/hw/intc/sifive_clint.h |  60 ----
 include/hw/intc/sifive_plic.h  |   4 +
 include/hw/riscv/sifive_u.h    |  14 +-
 include/hw/riscv/virt.h        |   2 +
 include/hw/timer/ibex_timer.h  |   2 +
 include/hw/timer/sifive_pwm.h  |  62 ++++
 target/riscv/cpu_bits.h        |  12 +-
 hw/dma/sifive_pdma.c           |  54 +++-
 hw/intc/ibex_plic.c            |  17 +-
 hw/intc/riscv_aclint.c         | 460 +++++++++++++++++++++++++++++
 hw/intc/sifive_clint.c         | 287 ------------------
 hw/intc/sifive_plic.c          |  30 +-
 hw/riscv/microchip_pfsoc.c     |  13 +-
 hw/riscv/opentitan.c           |  13 +-
 hw/riscv/shakti_c.c            |  16 +-
 hw/riscv/sifive_e.c            |  15 +-
 hw/riscv/sifive_u.c            |  68 ++++-
 hw/riscv/spike.c               |  16 +-
 hw/riscv/virt.c                | 654 ++++++++++++++++++++++++++++-------------
 hw/timer/ibex_timer.c          |  17 +-
 hw/timer/sifive_pwm.c          | 468 +++++++++++++++++++++++++++++
 target/riscv/cpu.c             |  31 ++
 target/riscv/cpu_helper.c      |   3 +-
 target/riscv/csr.c             |  26 +-
 hw/intc/Kconfig                |   2 +-
 hw/intc/meson.build            |   2 +-
 hw/riscv/Kconfig               |  13 +-
 hw/timer/Kconfig               |   3 +
 hw/timer/meson.build           |   1 +
 hw/timer/trace-events          |   6 +
 34 files changed, 1844 insertions(+), 669 deletions(-)
 create mode 100644 include/hw/intc/riscv_aclint.h
 delete mode 100644 include/hw/intc/sifive_clint.h
 create mode 100644 include/hw/timer/sifive_pwm.h
 create mode 100644 hw/intc/riscv_aclint.c
 delete mode 100644 hw/intc/sifive_clint.c
 create mode 100644 hw/timer/sifive_pwm.c

Comments

Richard Henderson Sept. 21, 2021, 8:49 p.m. UTC | #1 
On 9/20/21 11:53 PM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac:
> 
>    Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-09-20 16:17:05 +0100)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210921
> 
> for you to fetch changes up to ed481d9837250aa682f5156528bc923e1b214f76:
> 
>    hw/riscv: opentitan: Correct the USB Dev address (2021-09-21 12:10:47 +1000)
> 
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 6.2
> 
>   - ePMP CSR address updates
>   - Convert internal interrupts to use QEMU GPIO lines
>   - SiFive PWM support
>   - Support for RISC-V ACLINT
>   - SiFive PDMA fixes
>   - Update to u-boot instructions for sifive_u
>   - mstatus.SD bug fix for hypervisor extensions
>   - OpenTitan fix for USB dev address

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.

r~