diff mbox series

[PULL,23/36] Adjust min CPUID level to 0x12 when SGX is enabled

Message ID 20210906131059.55234-24-pbonzini@redhat.com
State New
Headers show
Series [PULL,01/36] target/i386: VMRUN and VMLOAD canonicalizations | expand

Commit Message

Paolo Bonzini Sept. 6, 2021, 1:10 p.m. UTC 
From: Sean Christopherson <sean.j.christopherson@intel.com>

SGX capabilities are enumerated through CPUID_0x12.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-16-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3b1f9cbdf6..2774550501 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6153,6 +6153,11 @@  void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
         if (sev_enabled()) {
             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
         }
+
+        /* SGX requires CPUID[0x12] for EPC enumeration */
+        if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
+            x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
+        }
     }
 
     /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */