@@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
TARGET_NEED_FDT=y
+TARGET_SWICHABLE_ENDIANNESS=y
@@ -2,3 +2,4 @@ TARGET_ARCH=arm
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
TARGET_NEED_FDT=y
+TARGET_SWICHABLE_ENDIANNESS=y
@@ -74,7 +74,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUARMState *env = &cpu->env;
uint32_t tmp;
- tmp = ldl_p(mem_buf);
+ tmp = gdb_read_reg32(mem_buf);
/* Mask out low bit of PC to workaround gdb bugs. This will probably
cause problems if we ever implement the Jazelle DBX extensions. */
@@ -47,7 +47,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUARMState *env = &cpu->env;
uint64_t tmp;
- tmp = ldq_p(mem_buf);
+ tmp = gdb_read_reg64(mem_buf);
if (n < 31) {
/* Core integer register. */
Apply new gdbstub interfaces we added previously to support both little and big endian guest debugging for ARM. And enable the TARGET_SWICHABLE_ENDIANNESS option. Signed-off-by: Changbin Du <changbin.du@gmail.com> --- configs/targets/aarch64-softmmu.mak | 1 + configs/targets/arm-softmmu.mak | 1 + target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-)