@@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ reg = env->pc;
+ ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+
+ for (i = 1; i < 32; i++) {
+ uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+ reg = env->gpr[i];
+ ret = kvm_set_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int kvm_riscv_get_regs_csr(CPUState *cs)
{
int ret = 0;
@@ -148,6 +173,69 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ reg = env->mstatus;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->mie;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->stvec;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->sscratch;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->sepc;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->scause;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->stval;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->mip;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->satp;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
+}
+
static int kvm_riscv_get_regs_fp(CPUState *cs)
{
int ret = 0;
@@ -181,6 +269,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -209,7 +331,24 @@ int kvm_arch_get_registers(CPUState *cs)
int kvm_arch_put_registers(CPUState *cs, int level)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_put_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_release_virq_post(int virq)