| Message ID | 20210813110149.1432692-3-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr | expand |
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> On Fri, Aug 13, 2021 at 7:02 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter > 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements > 48 virtual address bits in each 64-bit segment, not 40. > > Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/mips/cpu-defs.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index c6ab3af190e..cbc45fcb0e8 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -828,7 +828,7 @@ const mips_def_t mips_defs[] = > (0x1 << FCR0_D) | (0x1 << FCR0_S), > .CP1_fcr31 = 0, > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > - .SEGBITS = 42, > + .SEGBITS = 48, > .PABITS = 48, > .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | > ASE_LMMI | ASE_LEXT, > -- > 2.31.1 >
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index c6ab3af190e..cbc45fcb0e8 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -828,7 +828,7 @@ const mips_def_t mips_defs[] = (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 = 0, .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, + .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT,
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements 48 virtual address bits in each 64-bit segment, not 40. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)