Message ID | 20210711211057.2714586-5-f4bug@amsat.org |
---|---|
State | New |
Headers | show |
Series | [PULL,1/4] hw/sd/sdcard: When card is in wrong state, log which state it is | expand |
On 7/11/21 11:10 PM, Philippe Mathieu-Daudé wrote: > From: Joanne Koong <joannekoong@gmail.com> > > The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus capability > was added in v2. > > In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul << 28)) > where 28 represents the BUS64BIT SDHC_CAPAB field. > > Signed-off-by: Joanne Koong <joannekoong@gmail.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Message-Id: <20210623185921.24113-1-joannekoong@gmail.com> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > hw/sd/sdhci-internal.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h > index e8c753d6d1e..a76fc704e5e 100644 > --- a/hw/sd/sdhci-internal.h > +++ b/hw/sd/sdhci-internal.h > @@ -316,16 +316,16 @@ extern const VMStateDescription sdhci_vmstate; > * - 3.3v and 1.8v voltages > * - SDMA/ADMA1/ADMA2 > * - high-speed > + * - 64-bit system bus > * max host controller R/W buffers size: 512B > * max clock frequency for SDclock: 52 MHz > * timeout clock frequency: 52 MHz > * > * does not support: > * - 3.0v voltage > - * - 64-bit system bus > * - suspend/resume > */ > -#define SDHC_CAPAB_REG_DEFAULT 0x057834b4 > +#define SDHC_CAPAB_REG_DEFAULT 0x157834b4 > > #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ > DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ > Unfortunately this breaks the TYPE_IMX_USDHC model for which I don't have the datasheet, so I don't know how to fix it. I suppose it is simpler to remove the COMMON_PROPERTIES macro to avoid such problems.
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index e8c753d6d1e..a76fc704e5e 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -316,16 +316,16 @@ extern const VMStateDescription sdhci_vmstate; * - 3.3v and 1.8v voltages * - SDMA/ADMA1/ADMA2 * - high-speed + * - 64-bit system bus * max host controller R/W buffers size: 512B * max clock frequency for SDclock: 52 MHz * timeout clock frequency: 52 MHz * * does not support: * - 3.0v voltage - * - 64-bit system bus * - suspend/resume */ -#define SDHC_CAPAB_REG_DEFAULT 0x057834b4 +#define SDHC_CAPAB_REG_DEFAULT 0x157834b4 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \