diff mbox series

[3/4] target/alpha: Use tcg_constant_i64 for zero and lit

Message ID 20210708182519.750626-4-richard.henderson@linaro.org
State New
Headers show
Series target/alpha: Use tcg_constant_* | expand

Commit Message

Richard Henderson July 8, 2021, 6:25 p.m. UTC 
These constant temps do not need to be freed, and
therefore need less bookkeeping from tcg producers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/translate.c | 16 ++--------------
 1 file changed, 2 insertions(+), 14 deletions(-)

Comments

Philippe Mathieu-Daudé July 8, 2021, 7:10 p.m. UTC | #1 
On 7/8/21 8:25 PM, Richard Henderson wrote:
> These constant temps do not need to be freed, and
> therefore need less bookkeeping from tcg producers.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/alpha/translate.c | 16 ++--------------
>  1 file changed, 2 insertions(+), 14 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff mbox series

Patch

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 5ea091eef5..3fd66fb78d 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -67,8 +67,6 @@  struct DisasContext {
     /* Temporaries for $31 and $f31 as source and destination.  */
     TCGv zero;
     TCGv sink;
-    /* Temporary for immediate constants.  */
-    TCGv lit;
 };
 
 /* Target-specific return values from translate_one, indicating the
@@ -158,7 +156,7 @@  void alpha_translate_init(void)
 static TCGv load_zero(DisasContext *ctx)
 {
     if (!ctx->zero) {
-        ctx->zero = tcg_const_i64(0);
+        ctx->zero = tcg_constant_i64(0);
     }
     return ctx->zero;
 }
@@ -178,14 +176,6 @@  static void free_context_temps(DisasContext *ctx)
         tcg_temp_free(ctx->sink);
         ctx->sink = NULL;
     }
-    if (ctx->zero) {
-        tcg_temp_free(ctx->zero);
-        ctx->zero = NULL;
-    }
-    if (ctx->lit) {
-        tcg_temp_free(ctx->lit);
-        ctx->lit = NULL;
-    }
 }
 
 static TCGv load_gpr(DisasContext *ctx, unsigned reg)
@@ -201,8 +191,7 @@  static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg,
                          uint8_t lit, bool islit)
 {
     if (islit) {
-        ctx->lit = tcg_const_i64(lit);
-        return ctx->lit;
+        return tcg_constant_i64(lit);
     } else if (likely(reg < 31)) {
         return ctx->ir[reg];
     } else {
@@ -3024,7 +3013,6 @@  static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
 
     ctx->zero = NULL;
     ctx->sink = NULL;
-    ctx->lit = NULL;
 
     /* Bound the number of insns to execute to those left on the page.  */
     if (in_superpage(ctx, ctx->base.pc_first)) {