| Message ID | 20210706134457.81059-1-hnick@vmware.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint | expand |
On Tue, 6 Jul 2021 at 14:45, <hnick@vmware.com> wrote: > > Signed-off-by: Nick Hudson <hnick@vmware.com> > --- > target/arm/helper.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index a66c1f0b9e..910ace4274 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6326,11 +6326,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > .access = PL1_RW, .accessfn = access_tda, > .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), > .resetvalue = 0 }, > - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. > + /* > + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external > + * Debug Communication Channel is not implemented. > + */ > + { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, > + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, > + .access = PL0_R, .accessfn = access_tda, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + /* > + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as > + * it is unlikely a guest will care. > * We don't implement the configurable EL0 access. > */ > - { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, > - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, > + { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, > + .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, > .type = ARM_CP_ALIAS, > .access = PL1_R, .accessfn = access_tda, > .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, Applied to target-arm.next, thanks. -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index a66c1f0b9e..910ace4274 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6326,11 +6326,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .access = PL1_RW, .accessfn = access_tda, .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue = 0 }, - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + /* + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external + * Debug Communication Channel is not implemented. + */ + { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, + .access = PL0_R, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = 0 }, + /* + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as + * it is unlikely a guest will care. * We don't implement the configurable EL0 access. */ - { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, + { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, + .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, .type = ARM_CP_ALIAS, .access = PL1_R, .accessfn = access_tda, .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
Signed-off-by: Nick Hudson <hnick@vmware.com> --- target/arm/helper.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)