| Message ID | 20210706035015.122899-1-kito.cheng@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V | expand |
On 7/5/21 8:50 PM, Kito Cheng wrote: > Set I, M, A, F, D and C bit for hwcap if misa is set. > > V3 Changes: > - Simplify logic of getting hwcap. > > V2 Changes: > - Only set imafdc bits, sync with upstream linux kernel. > > Signed-off-by: Kito Cheng<kito.cheng@sifive.com> > --- > linux-user/elfload.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > Set I, M, A, F, D and C bit for hwcap if misa is set. > > V3 Changes: > - Simplify logic of getting hwcap. > > V2 Changes: > - Only set imafdc bits, sync with upstream linux kernel. These changelogs should not be in the commit message, but should be put below --- > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > --- > linux-user/elfload.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 598ab8aa13..42ef2a1148 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, > #define ELF_CLASS ELFCLASS64 > #endif > > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > +#define MISA_BIT(EXT) (1 << (EXT - 'A')) > + RISCVCPU *cpu = RISCV_CPU(thread_cpu); > + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + > + return cpu->env.misa & mask; > +#undef MISA_BIT > +} > + > static inline void init_thread(struct target_pt_regs *regs, > struct image_info *infop) > { Regards, Bin
Le 06/07/2021 à 05:50, Kito Cheng a écrit : > Set I, M, A, F, D and C bit for hwcap if misa is set. > > V3 Changes: > - Simplify logic of getting hwcap. > > V2 Changes: > - Only set imafdc bits, sync with upstream linux kernel. > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > --- > linux-user/elfload.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 598ab8aa13..42ef2a1148 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, > #define ELF_CLASS ELFCLASS64 > #endif > > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > +#define MISA_BIT(EXT) (1 << (EXT - 'A')) > + RISCVCPU *cpu = RISCV_CPU(thread_cpu); > + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + > + return cpu->env.misa & mask; > +#undef MISA_BIT > +} > + > static inline void init_thread(struct target_pt_regs *regs, > struct image_info *infop) > { > Applied to my linux-user-for-6.1 branch. (I have removed the history from the commit message) Thanks, Laurent
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 598ab8aa13..42ef2a1148 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #define ELF_CLASS ELFCLASS64 #endif +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ +#define MISA_BIT(EXT) (1 << (EXT - 'A')) + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + + return cpu->env.misa & mask; +#undef MISA_BIT +} + static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) {
Set I, M, A, F, D and C bit for hwcap if misa is set. V3 Changes: - Simplify logic of getting hwcap. V2 Changes: - Only set imafdc bits, sync with upstream linux kernel. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- linux-user/elfload.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)