diff mbox series

[05/11] target/ppc: moved ppc_store_lpcr to cpu.c

Message ID 20210512140813.112884-6-bruno.larsen@eldorado.org.br
State New
Headers show
Series target/ppc: add support to disable-tcg | expand

Commit Message

Bruno Larsen (billionai) May 12, 2021, 2:08 p.m. UTC
This function is used in !TCG cases, so it has been moved into a file
that is compiled when --disable-tcg is selected.

Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
 target/ppc/cpu.c         | 11 +++++++++++
 target/ppc/misc_helper.c | 10 ----------
 2 files changed, 11 insertions(+), 10 deletions(-)

Comments

Richard Henderson May 12, 2021, 5:07 p.m. UTC | #1
On 5/12/21 9:08 AM, Bruno Larsen (billionai) wrote:
> This function is used in !TCG cases, so it has been moved into a file
> that is compiled when --disable-tcg is selected.
> 
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> ---
>   target/ppc/cpu.c         | 11 +++++++++++
>   target/ppc/misc_helper.c | 10 ----------
>   2 files changed, 11 insertions(+), 10 deletions(-)

It's helpful to be more specific about where it's used -- not just !tcg, but 
the location.  In this case, hw/ppc/ during machine startup.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
David Gibson May 13, 2021, 3:53 a.m. UTC | #2
On Wed, May 12, 2021 at 11:08:07AM -0300, Bruno Larsen (billionai) wrote:
> This function is used in !TCG cases, so it has been moved into a file
> that is compiled when --disable-tcg is selected.
> 
> Signed-off-by: Bruno Larsen (billionai)
> <bruno.larsen@eldorado.org.br>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/cpu.c         | 11 +++++++++++
>  target/ppc/misc_helper.c | 10 ----------
>  2 files changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
> index 0ab7ac1af1..8a82e2ffa8 100644
> --- a/target/ppc/cpu.c
> +++ b/target/ppc/cpu.c
> @@ -24,6 +24,7 @@
>  #include "exec/log.h"
>  #include "fpu/softfloat-helpers.h"
>  #include "mmu-hash64.h"
> +#include "helper_regs.h"
>  
>  target_ulong cpu_read_xer(CPUPPCState *env)
>  {
> @@ -90,3 +91,13 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
>      /* FIXME: Should check for valid HTABMASK values in 32-bit case */
>      env->spr[SPR_SDR1] = value;
>  }
> +
> +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> +{
> +    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> +    CPUPPCState *env = &cpu->env;
> +
> +    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> +    /* The gtse bit affects hflags */
> +    hreg_compute_hflags(env);
> +}
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index b910ac6479..442b12652c 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -255,16 +255,6 @@ target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
>  /*****************************************************************************/
>  /* Special registers manipulation */
>  
> -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> -{
> -    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> -    CPUPPCState *env = &cpu->env;
> -
> -    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> -    /* The gtse bit affects hflags */
> -    hreg_compute_hflags(env);
> -}
> -
>  /*
>   * This code is lifted from MacOnLinux. It is called whenever THRM1,2
>   * or 3 is read an fixes up the values in such a way that will make
diff mbox series

Patch

diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 0ab7ac1af1..8a82e2ffa8 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -24,6 +24,7 @@ 
 #include "exec/log.h"
 #include "fpu/softfloat-helpers.h"
 #include "mmu-hash64.h"
+#include "helper_regs.h"
 
 target_ulong cpu_read_xer(CPUPPCState *env)
 {
@@ -90,3 +91,13 @@  void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
     /* FIXME: Should check for valid HTABMASK values in 32-bit case */
     env->spr[SPR_SDR1] = value;
 }
+
+void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
+{
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+    CPUPPCState *env = &cpu->env;
+
+    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
+    /* The gtse bit affects hflags */
+    hreg_compute_hflags(env);
+}
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index b910ac6479..442b12652c 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -255,16 +255,6 @@  target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 /*****************************************************************************/
 /* Special registers manipulation */
 
-void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
-{
-    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
-    CPUPPCState *env = &cpu->env;
-
-    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
-    /* The gtse bit affects hflags */
-    hreg_compute_hflags(env);
-}
-
 /*
  * This code is lifted from MacOnLinux. It is called whenever THRM1,2
  * or 3 is read an fixes up the values in such a way that will make