@@ -375,6 +375,7 @@ enum {
CPU_POWERPC_POWER9_DD20 = 0x004E1200,
CPU_POWERPC_POWER10_BASE = 0x00800000,
CPU_POWERPC_POWER10_DD1 = 0x00800100,
+ CPU_POWERPC_POWER10_DD20 = 0x00800200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
@@ -776,6 +776,8 @@
"POWER9 v2.0")
POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10,
"POWER10 v1.0")
+ POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
+ "POWER10 v2.0")
#endif /* defined (TARGET_PPC64) */
/***************************************************************************/
@@ -952,7 +954,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "power8", "power8_v2.0" },
{ "power8nvl", "power8nvl_v1.0" },
{ "power9", "power9_v2.0" },
- { "power10", "power10_v1.0" },
+ { "power10", "power10_v2.0" },
#endif
/* Generic PowerPCs */
@@ -9302,7 +9302,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
- (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_HAIL | LPCR_AIL |
LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
LPCR_DEE | LPCR_OEE))
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. The required change of the LPCR mask impacts all the POWER10 family. It is incorrect for DD1 but it does not break the modeling. Setting the HAIL bit is a requirement to support the scv instruction on PowerNV POWER10 platforms since glibc-2.33. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu-models.h | 1 + target/ppc/cpu-models.c | 4 +++- target/ppc/translate_init.c.inc | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-)