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03 May 2021 14:55:56 -0700 IronPort-SDR: hAAcGt5y5gmIKbIE2YjJk03LT1cyfxKc6mFJ5+42r3rLw1vxkHVqZoYSvyaKah/7pHwNTDu9tM LvlRxqo4Wc9S8l8hhx1VLgQaIqqNvLZTvOiRqrHjh2ZIIlyGFEAqpAUMYZSq1czYaqpGZEdqhw JeX35OtqwHAo+MtF9DQC76LsmfahFBIherm+ADLvLFueHlxwu+DvwF17LJ/YmFYgV2QR99L6SO Gas9IhMIFvCgJNB9IS8i4YeJ/P83HJTAJXMRBVLtVNMoxsALxtW+m/07+4ZBA0aVlHrNDCJnhC Iag= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.45]) by uls-op-cesaip01.wdc.com with ESMTP; 03 May 2021 15:15:42 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Date: Tue, 4 May 2021 08:13:23 +1000 Message-Id: <20210503221327.3068768-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210503221327.3068768-1-alistair.francis@wdc.com> References: <20210503221327.3068768-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=750139ea6=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com --- target/riscv/cpu_bits.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d98f3bc8bc..52640e6856 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -396,12 +396,6 @@ #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL -#if defined(TARGET_RISCV32) -#define HSTATUS_WPRI HSTATUS32_WPRI -#elif defined(TARGET_RISCV64) -#define HSTATUS_WPRI HSTATUS64_WPRI -#endif - #define HCOUNTEREN_CY (1 << 0) #define HCOUNTEREN_TM (1 << 1) #define HCOUNTEREN_IR (1 << 2)