| Message ID | 20210420013150.21992-1-frank.chang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions | expand |
On 4/19/21 6:31 PM, frank.chang@sifive.com wrote: > From: Frank Chang<frank.chang@sifive.com> > > In IEEE 754-2008 spec: > Invalid operation exception is signaled when doing: > fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) > unless c is a quiet NaN; if c is a quiet NaN then it is > implementation defined whether the invalid operation exception > is signaled. > > In RISC-V Unprivileged ISA spec: > The fused multiply-add instructions must set the invalid > operation exception flag when the multiplicands are Inf and > zero, even when the addend is a quiet NaN. > > This commit set invalid operation execption flag for RISC-V when > multiplicands of muladd instructions are Inf and zero. > > Signed-off-by: Frank Chang<frank.chang@sifive.com> > --- > fpu/softfloat-specialize.c.inc | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Alistair, will you take this via your riscv queue? r~
On Wed, Apr 21, 2021 at 12:17 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 4/19/21 6:31 PM, frank.chang@sifive.com wrote: > > From: Frank Chang<frank.chang@sifive.com> > > > > In IEEE 754-2008 spec: > > Invalid operation exception is signaled when doing: > > fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) > > unless c is a quiet NaN; if c is a quiet NaN then it is > > implementation defined whether the invalid operation exception > > is signaled. > > > > In RISC-V Unprivileged ISA spec: > > The fused multiply-add instructions must set the invalid > > operation exception flag when the multiplicands are Inf and > > zero, even when the addend is a quiet NaN. > > > > This commit set invalid operation execption flag for RISC-V when > > multiplicands of muladd instructions are Inf and zero. > > > > Signed-off-by: Frank Chang<frank.chang@sifive.com> > > --- > > fpu/softfloat-specialize.c.inc | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > Alistair, will you take this via your riscv queue? Yep, getting it now Alistair > > > r~ >
On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> + return 3; /* deafult NaN */
Late notice of spelling error: default.
r~
On Thu, Apr 22, 2021 at 11:06 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 4/19/21 6:31 PM, frank.chang@sifive.com wrote: > > + return 3; /* deafult NaN */ > > Late notice of spelling error: default. Fixed when I applied it. Thanks! Applied to riscv-to-apply.next Alistair > > r~ >
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c2f87addb25..12f29fbfc5e 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -624,6 +624,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } +#elif defined(TARGET_RISCV) + /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ + if (infzero) { + float_raise(float_flag_invalid, status); + } + return 3; /* deafult NaN */ #elif defined(TARGET_XTENSA) /* * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns