Message ID | 20210401181457.73039-5-vijai@behindbytes.com |
---|---|
State | New |
Headers | show |
Series | Add support for Shakti SoC from IIT-M | expand |
On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K <vijai@behindbytes.com> wrote: > > Connect one shakti uart to the shakti_c machine. > > Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> In future can you please keep the Reviewed by tags when sending a new version of the patch series? Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/shakti_c.c | 8 ++++++++ > include/hw/riscv/shakti_c.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c > index c8205d3f22..e207fa83dd 100644 > --- a/hw/riscv/shakti_c.c > +++ b/hw/riscv/shakti_c.c > @@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > SIFIVE_CLINT_TIMEBASE_FREQ, false); > > + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); > + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, > + shakti_c_memmap[SHAKTI_C_UART].base); > + > /* ROM */ > memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", > shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); > @@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj) > ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); > > object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); > + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); > > /* > * CPU type is fixed and we are not supporting passing from commandline yet. > diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h > index 8ffc2b0213..50a2b79086 100644 > --- a/include/hw/riscv/shakti_c.h > +++ b/include/hw/riscv/shakti_c.h > @@ -21,6 +21,7 @@ > > #include "hw/riscv/riscv_hart.h" > #include "hw/boards.h" > +#include "hw/char/shakti_uart.h" > > #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" > #define RISCV_SHAKTI_SOC(obj) \ > @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { > /*< public >*/ > RISCVHartArrayState cpus; > DeviceState *plic; > + ShaktiUartState uart; > MemoryRegion rom; > > } ShaktiCSoCState; > -- > 2.25.1 > >
---- On Fri, 02 Apr 2021 18:35:04 +0530 Alistair Francis <alistair23@gmail.com> wrote ---- > On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K <vijai@behindbytes.com> wrote: > > > > Connect one shakti uart to the shakti_c machine. > > > > Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> > > In future can you please keep the Reviewed by tags when sending a new > version of the patch series? Yes. My bad. Sorry about that. Thanks, Vijai Kumar K > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Alistair > > > --- > > hw/riscv/shakti_c.c | 8 ++++++++ > > include/hw/riscv/shakti_c.h | 2 ++ > > 2 files changed, 10 insertions(+) > > > > diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c > > index c8205d3f22..e207fa83dd 100644 > > --- a/hw/riscv/shakti_c.c > > +++ b/hw/riscv/shakti_c.c > > @@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) > > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > > SIFIVE_CLINT_TIMEBASE_FREQ, false); > > > > + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); > > + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { > > + return; > > + } > > + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, > > + shakti_c_memmap[SHAKTI_C_UART].base); > > + > > /* ROM */ > > memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", > > shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); > > @@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj) > > ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); > > > > object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); > > + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); > > > > /* > > * CPU type is fixed and we are not supporting passing from commandline yet. > > diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h > > index 8ffc2b0213..50a2b79086 100644 > > --- a/include/hw/riscv/shakti_c.h > > +++ b/include/hw/riscv/shakti_c.h > > @@ -21,6 +21,7 @@ > > > > #include "hw/riscv/riscv_hart.h" > > #include "hw/boards.h" > > +#include "hw/char/shakti_uart.h" > > > > #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" > > #define RISCV_SHAKTI_SOC(obj) \ > > @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { > > /*< public >*/ > > RISCVHartArrayState cpus; > > DeviceState *plic; > > + ShaktiUartState uart; > > MemoryRegion rom; > > > > } ShaktiCSoCState; > > -- > > 2.25.1 > > > > >
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index c8205d3f22..e207fa83dd 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); + /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); @@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); /* * CPU type is fixed and we are not supporting passing from commandline yet. diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index 8ffc2b0213..50a2b79086 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -21,6 +21,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/boards.h" +#include "hw/char/shakti_uart.h" #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" #define RISCV_SHAKTI_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + ShaktiUartState uart; MemoryRegion rom; } ShaktiCSoCState;
Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> --- hw/riscv/shakti_c.c | 8 ++++++++ include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 10 insertions(+)