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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/5] tcg: Elide memory barriers implied by the host memory model Date: Tue, 16 Mar 2021 16:07:33 -0600 Message-Id: <20210316220735.2048137-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reduce the set of required barriers to those needed by the host right from the beginning. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 76dc7d8dc5..c8501508c2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -102,8 +102,13 @@ void tcg_gen_mb(TCGBar mb_type) * (i.e. !(tb_cflags & CF_PARALLEL)), however, even with a single cpu * we have i/o threads running in parallel, and lack of memory order * can result in e.g. virtio queue entries being read incorrectly. + * + * That said, we can elide anything which the host provides for free. */ - tcg_gen_op1(INDEX_op_mb, mb_type); + mb_type &= ~TCG_TARGET_DEFAULT_MO; + if (mb_type & TCG_MO_ALL) { + tcg_gen_op1(INDEX_op_mb, mb_type); + } } /* 32 bit ops */