diff mbox series

target/m68k: implement rtr instruction

Message ID 20210307180730.471165-1-laurent@vivier.eu
State New
Headers show
Series target/m68k: implement rtr instruction | expand

Commit Message

Laurent Vivier March 7, 2021, 6:07 p.m. UTC
This is needed to boot MacOS ROM.

Pull the condition code and the program counter from the stack.

Operation:

    (SP) -> CCR
    SP + 2 -> SP
    (SP) -> PC
    (SP + 4) - > SP

This operation is not privileged.

Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target/m68k/translate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Laurent Vivier March 7, 2021, 6:20 p.m. UTC | #1
Le 07/03/2021 à 19:07, Laurent Vivier a écrit :
> This is needed to boot MacOS ROM.
> 
> Pull the condition code and the program counter from the stack.
> 
> Operation:
> 
>     (SP) -> CCR
>     SP + 2 -> SP
>     (SP) -> PC
>     (SP + 4) - > SP

This is in fact:

    SP + 4 -> SP

> 
> This operation is not privileged.
> 
> Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
>  target/m68k/translate.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index ac936ebe8f14..e6942955713c 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -2969,6 +2969,20 @@ DISAS_INSN(rtd)
>      gen_jmp(s, tmp);
>  }
>  
> +DISAS_INSN(rtr)
> +{
> +    TCGv tmp;
> +    TCGv ccr;
> +
> +    ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
> +    gen_set_sr(s, ccr, true);
> +    tcg_temp_free(ccr);
> +    tcg_gen_addi_i32(QREG_SP, QREG_SP, 2);
> +    tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
> +    tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
> +    gen_jmp(s, tmp);
> +}
> +
>  DISAS_INSN(rts)
>  {
>      TCGv tmp;
> @@ -6015,6 +6029,7 @@ void register_m68k_insns (CPUM68KState *env)
>      BASE(nop,       4e71, ffff);
>      INSN(rtd,       4e74, ffff, RTD);
>      BASE(rts,       4e75, ffff);
> +    INSN(rtr,       4e77, ffff, M68000);
>      BASE(jump,      4e80, ffc0);
>      BASE(jump,      4ec0, ffc0);
>      INSN(addsubq,   5000, f080, M68000);
>
diff mbox series

Patch

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ac936ebe8f14..e6942955713c 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2969,6 +2969,20 @@  DISAS_INSN(rtd)
     gen_jmp(s, tmp);
 }
 
+DISAS_INSN(rtr)
+{
+    TCGv tmp;
+    TCGv ccr;
+
+    ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
+    gen_set_sr(s, ccr, true);
+    tcg_temp_free(ccr);
+    tcg_gen_addi_i32(QREG_SP, QREG_SP, 2);
+    tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
+    tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
+    gen_jmp(s, tmp);
+}
+
 DISAS_INSN(rts)
 {
     TCGv tmp;
@@ -6015,6 +6029,7 @@  void register_m68k_insns (CPUM68KState *env)
     BASE(nop,       4e71, ffff);
     INSN(rtd,       4e74, ffff, RTD);
     BASE(rts,       4e75, ffff);
+    INSN(rtr,       4e77, ffff, M68000);
     BASE(jump,      4e80, ffc0);
     BASE(jump,      4ec0, ffc0);
     INSN(addsubq,   5000, f080, M68000);