diff mbox series

[PULL,05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

Message ID 20210305171515.1038-6-peter.maydell@linaro.org
State New
Headers show
Series [PULL,01/49] sbsa-ref: remove cortex-a53 from list of supported cpus | expand

Commit Message

Peter Maydell March 5, 2021, 5:14 p.m. UTC 
From: Rebecca Cran <rebecca@nuviainc.com>

Enable FEAT_SSBS for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..058672c9776 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2217,6 +2217,10 @@  static void arm_max_initfn(Object *obj)
         t = cpu->isar.id_pfr0;
         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = t;
+
+        t = cpu->isar.id_pfr2;
+        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+        cpu->isar.id_pfr2 = t;
     }
 #endif
 }